kactus2/kactus2dev

Issues

• SVD generator: redundant cluster layer

  #111 opened 24 days ago by hegza
  0

• Bug: false errors on duplicate on component instantiation parameter

  #110 opened a month ago by Kyrhe
  0

• Issue with port width evaluation formula with parenthesis

  #108 opened 4 months ago by Kyrhe
  0

• Bug: Crash on manual port editor cancellation

  #102 opened a month ago by Kyrhe
  1

• About the memory design supports UVM RAL 　

  #109 opened 2 months ago by YuTienL
  0

• Context Menu Options: "Open Containing Folder" and "Open XML File" Does not work on Linux

  #80 opened 4 months ago by AmeyaVS
  3

• Bug: copy of port type creates empty field

  #103 opened 4 months ago by Kyrhe
  1

• Running Kactus2 on CentOS 7

  #96 opened 4 months ago by abdullahyildiz
  1

• Bug: Mirrored interface of 22 standard in HW diagram editor shows wrong colour

  #104 opened 4 months ago by Kyrhe
  1

• Potential validator false error

  #107 opened 4 months ago by Kyrhe
  0

• Bug: bus definition wire presence displays wrong value in bus interface port map editor

  #106 opened 4 months ago by Kyrhe
  1

• BUG: Context menus open on different monitor

  #98 opened 5 months ago by Kyrhe
  0

• Bug: Adding generated files to fileset crashes upon trying to write verilog

  #105 opened 4 months ago by Kyrhe
  1

• Missing feature: Port wire editor / create ports from interface

  #99 opened 5 months ago by Kyrhe
  1

• BUG: Wiring from/to off-page wiring causes crash

  #100 opened 5 months ago by Kyrhe
  0

• BUG: Draft component bus type mirrors assigned incorrectly

  #101 opened 5 months ago by Kyrhe
  0

• Supporting alternate register

  #93 opened 5 months ago by DenizzzGuzell
  4

• After generating VHDL lib. collapses

  #89 opened 5 months ago by DenizzzGuzell
  2

• Missing Fields in Memory Maps Visualization

  #83 opened 5 months ago by pascal-creonic
  2

• make first execution Error

  #97 opened 5 months ago by Ryuji-Yatahagane
  2

• Shutting down unexpectedly

  #87 opened 6 months ago by DenizzzGuzell
  4

• Qt6 requires purchase by commercial users

  #95 opened 6 months ago by lmg260a
  2

• SVD generator guidelines.

  #92 opened 7 months ago by CalamaroS
  1

• How do I generate svd files

  #82 opened 7 months ago by Yaozzheng
  4

• Qhelgenerator and Qmake not found

  #91 opened 7 months ago by Ryuji-Yatahagane
  2

• Plugins are not available when using PythonAPI

  #90 opened 7 months ago by epekkar
  0

• Overriding component instance parameter from design is broken

  #81 opened 7 months ago by eyalherz
  1

• VHDL generation problems

  #88 opened 7 months ago by DenizzzGuzell
  2

• Bus definition wire port import / export problem

  #50 opened 2 years ago by TonyReinberger
  1

• Build failed with QT 6.6.0 with incomplete type ‘QSharedPointer<Design>

  #85 opened 8 months ago by vowstar
  1

• Support for 1685-2022

  #76 opened a year ago by scottven
  2

• VHDL component import misses the last port.

  #57 opened a year ago by TonyReinberger
  1

• Verilog Source Skeleton Code Generation Segmentation Fault.

  #75 opened a year ago by AmeyaVS
  3

• Kactus2 for Win64 3.11.1: Bundled Python should be 3.8 instead of 3.10

  #73 opened a year ago by gaudat
  1

• Unable to run the latest commit on the master branch

  #77 opened a year ago by AmeyaVS
  3

• Build & Install on MACOS

  #72 opened a year ago by abrahamktm
  1

• libIPXACTmodels.so.1

  #71 opened a year ago by Paul-Chaffey
  1

• deleting object of polymorphic class type 'SubspaceMapValidator' which has non-virtual destructor might cause undefined behavior [-Wdelete-non-virtual-dtor]

  #54 opened a year ago by olofk
  1

• Configuring VHDL Generator to use entity instantiation.

  #70 opened 2 years ago by andrewandrepowell
  1

• Unreasonable Python version dependency

  #66 opened 2 years ago by ktbarrett
  3

• kactus2 needs at least python3.8

  #65 opened 2 years ago by mkettn
  3

• Bus portmap autoconnect confuses PULLUP and PULLDN, but only sometimes.

  #61 opened 2 years ago by TonyReinberger
  1

• new release tag request: v3.9.333 is missing

  #62 opened 2 years ago by vowstar
  3

• Python interface library initialization

  #56 opened 2 years ago by olofk
  2

• Modern linux can't load executables as libraries

  #55 opened 2 years ago by olofk
  5

• Deleting bus definition wire ports breaks components.

  #59 opened 2 years ago by TonyReinberger
  1

• cannot use executable file libKactus2.so as input to a link

  #63 opened 2 years ago by vowstar
  2

• Verilog generation adds VHDL port type.

  #58 opened 2 years ago by TonyReinberger
  5

• Navigating components is very slow with 100s of ports.

  #51 opened 2 years ago by TonyReinberger
  4

• No rule to make target 'GeneratedFiles/moc_ComponentInstanceParameterFinder.cpp'

  #53 opened 2 years ago by olofk
  2