Pinned Repositories
apb4_mux
APB4 Multiplexor
APB_SLAVE
APB_SLAVE with open source Full DV environment
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Memory_Prj
SRAM project for Cache Coherency
nmigen-tutorial
A tutorial for using nmigen
pyuvm
The UVM written in Python
ravenoc
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
RDL_REG_GEN
RISCV_MYTH_SV
Labs from RISCV_MYTH training without TL Verilog but only using SV - COCOTB - YOSYS
pyuvm
The UVM written in Python
EngRaff92's Repositories
EngRaff92/APB_SLAVE
APB_SLAVE with open source Full DV environment
EngRaff92/ravenoc
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
EngRaff92/RDL_REG_GEN
EngRaff92/pyuvm
The UVM written in Python
EngRaff92/RISCV_MYTH_SV
Labs from RISCV_MYTH training without TL Verilog but only using SV - COCOTB - YOSYS
EngRaff92/yosys-cookbook
User-friendly explanation of Yosys options
EngRaff92/activecore
Hardware generation library based on "Kernel IP" (KIP) cores (microarchitectural programmable templates)
EngRaff92/apb
APB Logic
EngRaff92/apb_gpio
EngRaff92/assertion_rerun
Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
EngRaff92/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
EngRaff92/cocotb-test
Unit testing for cocotb
EngRaff92/common_cells
Common SystemVerilog components
EngRaff92/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
EngRaff92/EngRaff92_Hackathon
challenges-EngRaff92 forked
EngRaff92/Enigma_Machine_ICE40
Enigma Machine Project implemented on Icesugar Ice40 FPGA
EngRaff92/ice40-playground
Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)
EngRaff92/learn-fpga
Learning FPGA, yosys, nextpnr, and RISC-V
EngRaff92/mpsoc_example
EngRaff92/neoTRNG
:game_die: A Tiny and Platform-Independent True Random Number Generator for any FPGA.
EngRaff92/nerv
Naive Educational RISC V processor
EngRaff92/opentitan
OpenTitan: Open source silicon root of trust
EngRaff92/riscv-dv
Random instruction generator for RISC-V processor verification
EngRaff92/riscv-simple
Computer architecture learning environment using FPGAs
EngRaff92/riscv-simple-sv
A simple RISC V core for teaching
EngRaff92/riscv-tests
EngRaff92/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
EngRaff92/SIMPLE_RISCV
EngRaff92/the_verification_adventure
EngRaff92/Toast-RV32i
A Pipelined RISC-V RV32I Core in SystemVerilog