/activecore

Hardware generation library based on "Kernel IP" (KIP) cores (microarchitectural programmable templates)

Primary LanguageKotlinApache License 2.0Apache-2.0

ActiveCore

Making complex RTL designing rapid, fun, with full control and plenty of insights

Project description

ActiveCore is a framework that demonstrates original hardware designing concept based on "Kernel IP" (KIP) cores.

KIP core is a hardware generator that provides custom synthesizable execution kernel constructed in accordance to certain microarchitectural template. Each KIP core offers hardware description within custom computational model inferred from computational process organization inside hardware microarchitecture, applies microarchitecture-aware optimizations, and generates design specifications in standard RTL/HLS form.

KIP core's computational model is intended to include:

  • special data types with pre-defined order of initialization, assignment, and transfer of values;
  • auto-generated data structures and API for flow control, scheduling, communication, and synchronization "services" of the microarchitecture;
  • "microarchitecture-level" event model and handler procedures selectively exposed for behavioral-style programming of custom application functions and mechanisms.

Compared to other hardware generation frameworks, ActiveCore is constructed according to the following principles:

  • Dynamic generation of all hardware-related content, including data instances, structures, dimensions, expressions, procedural blocks, etc;
  • Decoupling generation logic from certain programming styles (e.g. functional one). ActiveCore relies on basic object-oriented capabilities, however, you can use any paradigm in your generators;
  • Reusing generic AST constructor/container of behavioral HW specifications (see hwast) for various KIP cores, with its content being fully accessible for analysis and manipulation.

The ultimate goal of the project is to provide top-down methodology and reusable components for explicit allocation of intermediate “microarchitectural middleware” design level for complex hardware. This design level (inspired by OS, VM, and various middleware in software stacks) decouples application-related logic from selected management mechanisms of hardware microarchitectures, addressing:

  • rapid design of functionally differentianted IP blocks with common microarchitectural mechanisms;
  • diversification of responsibility and competence of IP engineers: implementation of engines offering key microarchitectural mechanisms can be charged to the core of leading expert engineers, while developers of final designs can focus solely on application-specific functionality;
  • facilitating IP design centers to package, reuse and deliver basis for semi-custom IP cores, enabling seamless reuse of microarchitectural competence for unique, highly specialized designs.

pic_test

Aligned to the strategy of e.g. RISC-V project that standardises open (or provides a baseline for) RISC CPU architecture, ActiveCore endeavours to propose open reference implementations of common microarchitectures (decoupled from certain architecture).

Project structure

Current version of project is implemented as a collection of standalone Kotlin libraries that can be built using IntelliJ IDEA: pic_test

  • hwast - generic AST constructor of behavioral-style HW specifications (/hwast)

  • Demo KIP cores based on hwast (/kernelip):

    • Rtl - generator of behavioral RTL. Exports to SystemVerilog HDL
    • Cyclix (cyclic execution) - generator of hardware performing cyclic statically scheduled computations. Translates either to synchronous RTL for Rtl KIP or to C++ sources for Xilinx HLS pic_test
    • Pipex (pipelined execution) - generator of hardware with dynamically scheduled scalar in-order pipelined microarchitecture. Supports inter-stage communication and variable-latency I/O synchronization features. Translates to Cyclix KIP. Close analogue (but implemented differently): TL-Verilog project pic_test
    • Reordex (reordered execution) - generator of (co)processors with superscalar out-of-order (OoO) microarchitecture and register renaming. Translates to Cyclix KIP pic_test

  • Demo core generators based on KIP cores (/designs/coregen):

    • Taylor - sine wave generator demonstrating usage of stalling and credit-based flow control mechanisms, based on Pipex KIP core. Location: /designs/rtl/credit_test
    • Aquaris - RISC-V CPU generator with varying-length pipelines (RV32I, 1-6 pipeline stages), based on Pipex KIP core pic_test
    • Ariele - full xbar generator, based on Pipex KIP core
    • Citadel - OoO FPU coprocessor, based on Reordex KIP core (needs actualization)
    • Agenda - OoO RISC-V (RV32I) CPU, based on Reordex KIP core (passes basic tests, optimization in progress) pic_test

  • Auxiliary reusable cores:

    • UDM - bus transactor controlled via UART interface. Supports bursts and bus timeouts. Communication library for Python 3 included. Lab work manual included: https://github.com/AntonovAlexander/activecore/blob/master/designs/rtl/udm/doc/udm_lab_manual.pdf. Location: /designs/rtl/udm
    • sigma_tile - basic CPU tile consisting of a single Aquaris RISC-V core, tightly coupled scratchpad RAM with single-cycle delay, interrupt controller, timer, Host InterFace (HIF), and eXpansion InterFace (XIF). HIF and XIF protocols are equivalent to UDM bus protocol. Location: /designs/rtl/sigma_tile
    • kerygma_tile - sigma_tile equivalent based on 2-wide superscalar Agenda CPU core and 2-bank RAM. Location: /designs/rtl/kerygma/hw

  • Demo FPGA-based SoCs:

Publications