Issues
- 4
Multiple analysis (imp)ports in a scoreboard
#202 opened by marcorogo13 - 1
Add UVM Register Access Sequences
#197 opened by eminakgun - 2
- 3
Any example that mimics uvm_component_param_utils?
#193 opened by sbhutada - 3
pyuvm + latest cocotb: Decorator and LogicArray
#192 opened by LeoGoTi - 4
Problems with scoreboard
#188 opened by hurisson - 5
Any insights on PyUVM vs UVM-Python
#191 opened by sbhutada - 4
Accessing pyuvm/cocotb from custom build infra
#190 opened by sbhutada - 1
- 2
Reconsidering Python Assertions for Run-Time Checks
#187 opened by hzisman - 9
uvm_driver uses uvm_sequence_item_port instead of uvm_seq_item_pull_port
#184 opened by timothyscherer - 42
Add register classes
#6 opened by tudortimi - 4
Passing arrays from Monitor to Scoreboard
#180 opened by davidp135 - 5
Implementation of runtime phases
#179 opened by timothyscherer - 0
Replace fork with start_soon in tests.py
#160 opened by raysalemi - 3
Running pyuvm tests with pytest
#156 opened by timothyscherer - 6
Add support for cocotb TESTCASE specifier
#152 opened by timothyscherer - 0
Use start_soon in place for fork --> examples/TinyAlu
#128 opened by svenka3 - 1
Support simulation time in transactions
#72 opened by raysalemi - 1
- 1
Segmentation error in cocotb+vcs sim env
#144 opened by linyx94 - 0
ValueError when using cocotb v1.8.0.dev0
#140 opened by mmichilot - 7
- 2
Using tox with Python 3.6/3.9 etc.
#122 opened by svenka3 - 0
Simple typo in Makefile
#121 opened by svenka3 - 13
TinyAlu example on Windows - error on class_
#113 opened by svenka3 - 4
Test tests/cocotb_tests/t12_tlm is hanging
#116 opened by raysalemi - 2
- 2
- 0
@pyuvm.test does not work with TESTCASE
#109 opened by miserva - 1
Add TLM methods to uvm_tlm_fifo_base
#107 opened by miserva - 2
The lack of `*_imp` classes
#106 opened by miserva - 8
- 0
- 7
Simplify making tests
#89 opened by ktbarrett - 8
- 2
TinyALU VHDL example does not work
#85 opened by jonpovey - 1
Fix Scoreboard in examples
#81 opened by raysalemi - 0
Clear singletons on run_test
#61 opened by raysalemi - 0
Add tests for analysis ports
#23 opened by raysalemi - 1
Restructure `uvm_*_exports` to be the base of `uvm_*_port` so that only port has the connect function
#35 opened by raysalemi - 2
- 4
When I change the simulator to Modelsim: "make sim" hangs [On Windows computer]
#14 opened by Eulerianial - 2
flake8 on tests?
#11 opened by raysalemi - 10
Steps to use development version of `pyuvm` could make use of `pip install -e`
#7 opened by tudortimi - 8
Use `pytest` as a testing framework
#8 opened by tudortimi - 17
- 1
- 1
- 2
Where is the package "tb_pkg "in the example?
#1 opened by gyx3598