Juniper/open-register-design-tool

Is there an option to enable address channel for each write and read, instead of one address channel?

kongty opened this issue · 0 comments

Currently, when addressing mode is either leaf or parallel, generated RTL has only one address channel which write operation and read operation shares. (e.g. h2d_pio_dec_address)

Is there an option (or future plan to support) to enable having two channels for write_address and read_address? (e.g. h2d_pio_dec_wr_address and h2d_pio_dec_rd_address)
I don't see any issues to support it.