Pinned Repositories
awesome-open-hardware-verification
A List of Free and Open Source Hardware Verification Tools and Frameworks
croyde-riscv
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
doxygen-themes
A collection of the various Doxygen Theme customisations I have created and used.
uart
A simple implementation of a UART modem in Verilog.
verilog-dot
A simple dot file / graph generator for Verilog syntax trees.
verilog-parser
A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
verilog-vcd-parser
A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
riscv-crypto
RISC-V cryptography extensions standardisation work.
scarv-cpu
SCARV: a side-channel hardened RISC-V platform
xcrypto
XCrypto: a cryptographic ISE for RISC-V
ben-marshall's Repositories
ben-marshall/awesome-open-hardware-verification
A List of Free and Open Source Hardware Verification Tools and Frameworks
ben-marshall/verilog-parser
A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
ben-marshall/uart
A simple implementation of a UART modem in Verilog.
ben-marshall/verilog-vcd-parser
A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
ben-marshall/croyde-riscv
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
ben-marshall/verilog-dot
A simple dot file / graph generator for Verilog syntax trees.
ben-marshall/doxygen-themes
A collection of the various Doxygen Theme customisations I have created and used.
ben-marshall/microcoder
Define custom assembly-like instructions and use them to write programs which are transpiled into synthesisable Verilog code.
ben-marshall/verilog-doc
A basic documentation generator for Verilog, similar to Doxygen.
ben-marshall/verilog-probe
A very small and simple debug probe designed to be very easy to interface with and be usable via SPI, JTAG and UART.
ben-marshall/tim
A small CPU core complete with compiler and ISA specification. Eventually....
ben-marshall/aes-sboxes
Somewhere to put different implementations of the AES SBox
ben-marshall/riscv-multi-cycle
WIP - A multi-cycle implementation of the RISCV rv32ui architecture. *unverified, use PicoRV32 instead!*
ben-marshall/vanilla-riscv
Vanilla RISC-V core, implementing RV32IMC
ben-marshall/ann-playground
Code I develop while learning about Artificial Neural Networks
ben-marshall/latex-boilerplate
A simple latex boilerplate with makefile for common commands.
ben-marshall/SILVER
SILVER - Statistical Independence and Leakage Verification
ben-marshall/awesome-semiconductor-startups
List of awesome semiconductor startups
ben-marshall/ben-marshall.github.io
My personal website, such as it is.
ben-marshall/configuration-structure
RISC-V Configuration Structure
ben-marshall/cssbristol.github.io
Source code for the UoB Computer Science Society web portal
ben-marshall/riscv-arch-test
ben-marshall/riscv-bitmanip
Working draft of the proposed RISC-V Bitmanipulation extension
ben-marshall/riscv-isa-sim
Spike, a RISC-V ISA Simulator
ben-marshall/riscv-opcodes
RISC-V Opcodes
ben-marshall/riscv-tests
ben-marshall/riscv-zkt-list
Zkt "safe list": extension attests that the machine has data-independent execution time for these instructions
ben-marshall/sail-riscv
Sail RISC-V model
ben-marshall/sat-solver
A simple combinatorial boolean sat solver based on the AC-3 Algorithm