RISC-V

docs-dev-guide

Documentation developer guide

docs-resources

docs-spec-template

meta-riscv

OpenEmbedded/Yocto layer for RISC-V Architecture

riscv-crypto

RISC-V cryptography extensions standardisation work.

riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

riscv-isa-manual

RISC-V Instruction Set Manual

riscv-opcodes

RISC-V Opcodes

riscv-v-spec

Working draft of the proposed RISC-V V vector extension

sail-riscv

Sail RISC-V model

riscv/riscv-isa-manual

RISC-V Instruction Set Manual

riscv/riscv-opcodes

RISC-V Opcodes

riscv/riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

riscv/sail-riscv

Sail RISC-V model

riscv/meta-riscv

OpenEmbedded/Yocto layer for RISC-V Architecture

riscv/learn

Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.

riscv/riscv-fast-interrupt

Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)

riscv/riscv-j-extension

Working Draft of the RISC-V J Extension Specification

riscv/riscv-profiles

RISC-V Architecture Profiles

riscv/riscv-cfi

This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.

riscv/docs-dev-guide

Documentation developer guide

riscv/riscv-aia

riscv/configuration-structure

RISC-V Configuration Structure

riscv/riscv-cheri

This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.

riscv/riscv-smmtt

This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.

riscv/docs-spec-template

riscv/docs-resources

riscv/riscv-double-trap

RISC-V Double Trap Fast-Track Extension

riscv/riscv-zabha

The Zabha extension provides support for byte and halfword atomic memory operations.

riscv/riscv-docs-base-container-image

A base container image populated with the dependencies to build the RISC-V Documentation.

riscv/riscv-glossary

riscv/riscv-zilsd

Zilsd (Load/Store Pair for RV32) Fast-Track Extension

riscv/riscv-b

"B" extension - that represents the collection of the Zba, Zbb, and Zbs extensions

riscv/riscv-zaamo-zalrsc

Zaamo / Zalrsc: A extension components

riscv/riscv-svvptc

Obviating Memory-Management Instructions after Marking PTEs Valid (Svvptc)

riscv/riscv-performance-events

RISC-V Performance Events Specification

riscv/riscv-zalasr

The ISA specification for the Zalasr extension.

riscv/composable-extensions

This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.

riscv/riscv-memory-tagging

Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores

riscv/riscv-performance-sampling

Define 2 new extensions to, along with Zihpm and Sscofpmf, enable event and instruction sampling with precise attribution.