Issues
- 0
Should HLVX effect vsstatus.SUM?
#1480 opened by Wangrodman - 0
Many line breaks in code of vector chapter
#1479 opened by demin-han - 5
zext.h and packw are both real instructions with overlapping encodings
#1475 opened by tariqkurd-repo - 5
- 8
- 0
make build-epub failed
#1468 opened by demin-han - 3
Do the following PMA changes of implicit PTE access need xFENCE to synchronize?
#1392 opened by terranfund - 2
Fix table issues
#1403 opened by kersten1 - 2
What will happen if a hart executes `sinval.vma` with no fence before `sfence.w.inval`
#1423 opened by huxuan0307 - 3
Are single-operand instructions R or I-type?
#1465 opened by davidharrishmc - 7
Can the value of time CSR be a lagged value of mtime?
#1438 opened by zhuotianshu - 0
- 0
merge and release is broken
#1461 opened by wmat - 0
Fix broken references to instruction definitions.
#1458 opened by wmat - 1
use docs-resources as submodule to pull in shared resources (pdf theme, fonts, etc)
#1448 opened by kbroch-rivosinc - 0
Fix merge and release workflow
#1454 opened by wmat - 1
funct7 values of SRA,SUBW,SRAW appear to be incorrect in unpriv section 4.2.2 of version 20240411.
#1452 opened by puyogo-suzuki - 2
Question about `senvcfg` and `henvcfg` when V=1
#1445 opened by lfiolhais - 1
- 5
Should Vector chapter version be bumped to 2.0?
#1402 opened by wmat - 3
- 3
- 0
Fix GitHub workflows to use new filenames.
#1441 opened by wmat - 2
Publish nightly draft to RISC-V's Github Pages
#1427 opened by VitalyAnkh - 3
Update generated filenames to be more desciptive.
#1437 opened by wmat - 0
Remove the word asciidoc from generated docs file names.
#1435 opened by wmat - 11
- 1
Svadu chapter in Privileged arch spec is missing details
#1426 opened by kdockser - 2
- 9
Does mcountinhibit Inhibit Only Unprivileged Counters, or Both Machine and Unprivileged Counters?
#1420 opened by cebarobot - 4
privileged isa spec. table 3 read-only csr's
#1421 opened by farukyld - 2
Sstc description hasn't been merged well
#1418 opened by tariqkurd-repo - 5
Zawrs: "These instructions are not supported in a constrained LR/SC loop."
#1409 opened by tariqkurd-repo - 8
Don't write in prose
#1396 opened by Timmmm - 7
- 1
PMM field in mseccfg register
#1407 opened by atishp04 - 0
I think this is still just partially solved. `Zbkc`, and even `Zba` (and many other) extensions continue to have:
#1404 opened by wmat - 2
Formatting issues in version 20240411
#1394 opened by aswaterman - 2
- 2
Clarify PBMT and PBMTE rule when implicit memory access for VS-stage address translation
#1377 opened by Wangrodman - 2
Question: How are pending software interrupts delegated to Supervisor when mstatus.SIE is unset handled ?
#1393 opened by iamkarthikbk - 0
Add links / tags for each statement
#1397 opened by Timmmm - 0
Merge privileged and unprivileged specs
#1395 opened by Timmmm - 3
- 2
How to clear hvip.VSEIP when hvip.VSEIP is asserted and VS-level exteranl interrupt is delegated to VS-mode?
#1384 opened by jinyinghan324 - 0
Semantics of using reserved encodings; constraints on unspecified behavior
#1389 opened by aswaterman - 4
does Xtvec need to support all invalid adddresses?
#1385 opened by tariqkurd-repo - 0
Realign bytefield images
#1386 opened by kersten1 - 3
Does misaligned exception in nottaken branches cause an exception?
#1379 opened by omerguzelelectronicguy - 1
How to clear hvip.VSEIP when VS-level extenal interrupt is delegated to VS level?
#1383 opened by jinyinghan324