Issues
- 1
Zcmp depends on ABI register names, which are no longer introduced in unprivileged manual
#1376 opened - 0
Chapter 9.1 nit
#1374 opened - 2
Chapter 7.1 issues
#1372 opened - 3
hyphenated exception names?
#1370 opened - 2
Plans for SAIL code integration?
#1369 opened - 3
ISA Specification Consolidation: Unprivileged Architecture Version 20240411, Introduction
#1368 opened - 0
Priv spec chapter 5 italics issues
#1367 opened - 7
ISA Specification Consolidation - review comment on volumes 1 and 2 menvcfg register information consistency
#1366 opened - 2
Is it necessary to store ASID in the PTE cache?
#1363 opened - 1
bf16 chapter should be after zfh chapter
#1362 opened - 0
- 2
Too many chapters
#1360 opened - 12
Rules for CSR and register usage
#1355 opened - 4
Ordering of names in titles
#1352 opened - 2
- 1
`zext.w` should not exist in `Zba` group
#1350 opened - 4
Inconsistency for Shift instructions in RV64I
#1349 opened - 2
- 0
Fields encoding in sip/sie Csr Register
#1347 opened - 3
- 3
- 1
Name of CSR jvt is not capitalized
#1343 opened - 2
Is Ssqosid in Priv 1.13 or 1.14?
#1341 opened - 5
Some state-enable text should be normative.
#1340 opened - 1
- 0
- 0
- 0
- 1
For implementation with TLB, if a virtual address hit both 2M-pte and 4K-pte, shoud page fault arise?
#1328 opened - 1
CSR tables in Priv Ch. 2 are misformatted
#1322 opened - 5
- 13
`Zbc` missing from `B` extension description?
#1314 opened - 16
- 9
- 4
- 1
- 0
- 2
- 4
Fix duplication of zbkb, zbkc, zbkx.
#1298 opened - 4
Userspace unique CPU identifier
#1297 opened - 1
Update Preface to include new chapters.
#1296 opened - 0
- 0
Broken reference to a table in smcdeleg chapter.
#1291 opened - 2
- 2
W[13]
#1302 opened - 0
Update unpriv intro
#1284 opened - 4
more chapter re-ordering
#1282 opened - 8
MMWP name violates friendly language policy
#1280 opened - 2
Maybe wrong fr edge in litmus sample?
#1269 opened - 1
software need for 16-byte atomic loads
#1537 opened