riscv/riscv-isa-manual

An inquiry regarding the execution requirements of the vector extension.

Codemaker-1 opened this issue · 2 comments

Codemaker-1 commented

Hi,

In M-mode, the execution of the vector extension requires setting the vs bit in mstatus. Does vsstatus also need to be set?

Thank you!

gfavor commented

See section 3.3 of the RVV spec.

Codemaker-1 commented

I see, thank you very much!