gfavor

riscv-isa-manual

RISC-V Instruction Set Manual

integrated-matrix-extension

Administrative repository for the Integrated Matrix Extension Task Group

riscv-ras-eri

The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and configuring means to report the error to a handler component.

server-soc

The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.

riscv-config

RISC-V Configuration Validator

riscv-aclint

riscv-debug-spec

Working Draft of the RISC-V Debug Specification Standard

riscv-isa-manual

RISC-V Instruction Set Manual

riscv-svadu

The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.

gfavor/riscv-isa-manual

RISC-V Instruction Set Manual