riscv/riscv-isa-manual

Zawrs: "These instructions are not supported in a constrained LR/SC loop."

tariqkurd-repo opened this issue · 5 comments

The description for Zawrs says These instructions are not supported in a constrained LR/SC loop.

What does this mean exactly?

Should the core detect that they are within an LR/SC loop and take an illegal exception, or ignore them, or what?

Please clarify

It means that if a WRS.* instruction is in a LR/SC loop then it is not a constrained LR/SC loop and guarantees around eventual success of store-conditional does not apply. This instruction is not part of the set of instructions listed in section 14.3 as supported in a constrained LR/SC loop.

This is all just a matter of clarification, but can’t we just delete this clause altogether? The A chapter already excludes these new instructions from constrained loops by not mentioning them.

ok - got it - it's because the spec was developed separately and so that statement was needed in a separate doc but not now it's merged - so yes it sounds like it could be deleted - or just adding an xref to the definition of a constrained LR/SC loop would also make it clear.

No, the statement was always superfluous. The constrained LR/SC loop definition already precludes new instructions by virtue of admitting a restricted set and excluding all others.

Update in PR #1416