Pinned Repositories
iommu-docs
iommu-reference
iommu-rtl
RISC-V IOMMU in verilog
linux
Linux kernel source tree
opentitan
OpenTitan: Open source silicon root of trust
qemu
Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
riscv-acpi-iommu
riscv-cfi
This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.
riscv-iommu
The repo will be used to hold the draft non-ISA IOMMU specification under codevelopment by the IOMMU TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.
riscv-server-platform
RISC-V Server Plaftorm
ved-rivos's Repositories
ved-rivos/riscv-cfi
This repo holds the work area and revisions of the RISC-V CFI (Shadow Stack and Landing Pads) specifications. CFI defines the privileged and unprivileged ISA extensions that can be used by privileged and unprivileged programs to protect the integrity of their control-flow.
ved-rivos/riscv-iommu
The repo will be used to hold the draft non-ISA IOMMU specification under codevelopment by the IOMMU TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.
ved-rivos/riscv-server-platform
RISC-V Server Plaftorm
ved-rivos/linux
Linux kernel source tree
ved-rivos/opentitan
OpenTitan: Open source silicon root of trust
ved-rivos/qemu
Official QEMU mirror. Please see https://www.qemu.org/contribute/ for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
ved-rivos/riscv-arch-test
ved-rivos/riscv-b
"B" extension - that represents the collection of the Zba, Zbb, Zbs extensions
ved-rivos/riscv-cmqri
This repo holds the work area and revisions of a QoS register interface for caches and memory controllers specification. The QoS register interface is a non-ISA specification that supports configuring resource allocations to applications and monitoring the resource usage by applications.
ved-rivos/riscv-config
RISC-V Configuration Validator
ved-rivos/riscv-ctg
ved-rivos/riscv-debug-spec
Working Draft of the RISC-V Debug Specification Standard
ved-rivos/riscv-double-trap
RISC-V Double Trap Fast-Track Extension
ved-rivos/riscv-isa-manual
RISC-V Instruction Set Manual
ved-rivos/riscv-isa-sim
Spike, a RISC-V ISA Simulator
ved-rivos/riscv-opcodes
RISC-V Opcodes
ved-rivos/riscv-profiles
RISC-V Architecture Profiles
ved-rivos/riscv-ras-eri
The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and configur
ved-rivos/riscv-security-model
RISC-V Security Model
ved-rivos/riscv-smmtt
This specification will define the Smmtt privilege ISA extensions required to support the supervisor domain isolation for many isolation use cases e.g. confidential-computing, fault isolation and so on.
ved-rivos/riscv-ssqosid
This repo will hold the specification for the proposed QoS ID extension being pursued on the fast-track process.
ved-rivos/riscv-svadu
The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.
ved-rivos/riscv-svvptc
Obviating Memory-Management Instructions after Marking PTEs Valid (Svvptc)
ved-rivos/riscv-tests
ved-rivos/riscv-zaamo-zalrsc
Zaamo / Zalrsc: A extension components
ved-rivos/riscv-zabha
The Zabha extension provides support for byte and halfword atomic memory operations.
ved-rivos/riscv-zacas
riscv-zacas created from docs-spec-template template
ved-rivos/sail-riscv-cfi
Sail RISC-V model
ved-rivos/server-soc
The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.
ved-rivos/tg-nexus-trace
RISC-V Nexus Trace TG documentation and reference code