Pinned Repositories
cheri-exercises
Learning exercises for CHERI
cheri-specification
CHERI ISA Specification
core-v-docs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
cv32e41p
4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
docs-style-guide
Documentation Style Guide for all projects under the Pylons Project
groups
RISC-V Technical Working Groups - charter, meeting minutes, planning documents
riscv-bitmanip
Working draft of the proposed RISC-V Bitmanipulation extension
riscv-cheri
This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
riscv-rv32zild
Proposal for a RISC-V extension allowing the use of 64-bit load/store operations in a 32-bit (RV32) architecture
tariqkurd-repo's Repositories
tariqkurd-repo/riscv-rv32zild
Proposal for a RISC-V extension allowing the use of 64-bit load/store operations in a 32-bit (RV32) architecture
tariqkurd-repo/cheri-exercises
Learning exercises for CHERI
tariqkurd-repo/cheri-specification
CHERI ISA Specification
tariqkurd-repo/core-v-docs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
tariqkurd-repo/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
tariqkurd-repo/cv32e41p
4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
tariqkurd-repo/docs-style-guide
Documentation Style Guide for all projects under the Pylons Project
tariqkurd-repo/groups
RISC-V Technical Working Groups - charter, meeting minutes, planning documents
tariqkurd-repo/riscv-bitmanip
Working draft of the proposed RISC-V Bitmanipulation extension
tariqkurd-repo/riscv-cheri
This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
tariqkurd-repo/riscv-code-size-reduction
tariqkurd-repo/riscv-isa-manual
RISC-V Instruction Set Manual
tariqkurd-repo/riscv-opcodes
RISC-V Opcodes
tariqkurd-repo/riscv-p-spec
RISC-V Packed SIMD Extension
tariqkurd-repo/riscv-tee
tariqkurd-repo/rock-the-jvm
example code form the udemy scala training course