riscv/riscv-isa-manual

How to clear hvip.VSEIP when hvip.VSEIP is asserted and VS-level exteranl interrupt is delegated to VS-mode?

jinyinghan324 opened this issue · 2 comments

If VS-level external interrupt is asserted because hvip.VSEIP is asserted and VS-level exteranl interrupt is delegated to VS-mode, then interrupt hanlder runs in VS-mode and hvip cannot be written. How to clear hvip.VSEIP in handler?

Thinking about how this works without virtualization: normally the supervisor external interrupt handler would claim an interrupt from the PLIC by doing an MMIO access, which as a side effect would cause the PLIC to deassert the interrupt line, making sip.SEIP become 0.

The analogous thing with virtualization would be that the hypervisor is emulating a PLIC for the guest OS. When the guest OS executes the MMIO access to claim an interrupt from the PLIC, that MMIO access will trap into the hypervisor so that it can emulate the access. The hypervisor's emulation routine then has the opportunity to clear hvip.VSEIP.

I should add: I think this is only interesting in the case that the hypervisor is emulating an interrupt controller for the guest. If the guest has access to a real interrupt controller, then hvip.VSEIP would not be used, and so there would be no need to clear it.