riscv/riscv-isa-manual

Clarify PBMT and PBMTE rule when implicit memory access for VS-stage address translation

Wangrodman opened this issue · 2 comments

Wangrodman commented

Although the leaf PTE is not a stage leaf PTE, the specification does not explicitly assign meaning to PBMT in this scenario. Please clarify the following two questions::

  1. Does the leaf PTE's PBMT of implicit memory access for VS-stage address translation affect the memory attribute of accessing the guest's PTE?
  2. If the answer to Q1 is YES, which PBMTE, menvcfg or henvcfg, controls the PBMT?"
gfavor commented

#1. The last paragraph of the Svpbmt spec specifies the behavior for two-stage translations. In general PBMTs don't affect the PMAs for page tables and the implicit accesses to them. They only affect the final explicit access after the access's VA has been translated to a PA.

Wangrodman commented

#1. The last paragraph of the Svpbmt spec specifies the behavior for two-stage translations. In general PBMTs don't affect the PMAs for page tables and the implicit accesses to them. They only affect the final explicit access after the access's VA has been translated to a PA.

Got it, no further question.