Pinned Repositories
AXIS-Async-FIFO
parameterized AXIS FIFO design
CDC_FIFO_Design
Multi-bit Synchronization across Clock Domains
EthernetTimeSynchronizer
FFT-Computation
Fast Fourier Transform (FFT) algorithm computes the discrete Fourier transform (DFT) of a sequence, or its inverse (IFFT)
Low-Speed-Controllers
I2C, SPI, UART memory bridge
MxN-cross-bar-switch
Axis based MxN cross bar switch implementation
NAND-Flash-Controller
2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
PCIe-Controller
PCI Express ® Base Specification Revision 3.0
Tool-Make-Script
Synopsys Design compiler, VCS and Tetra-MAX
Tri-Mode-Ethernet-MAC-10-100-1000-
Ethernet-MAC System verilog
jomonkjoy's Repositories
jomonkjoy/Tool-Make-Script
Synopsys Design compiler, VCS and Tetra-MAX
jomonkjoy/Tri-Mode-Ethernet-MAC-10-100-1000-
Ethernet-MAC System verilog
jomonkjoy/CDC_FIFO_Design
Multi-bit Synchronization across Clock Domains
jomonkjoy/NAND-Flash-Controller
2, 4, 8Gb: x8/x16 Multiplexed NAND Flash Memory
jomonkjoy/PCIe-Controller
PCI Express ® Base Specification Revision 3.0
jomonkjoy/Low-Speed-Controllers
I2C, SPI, UART memory bridge
jomonkjoy/MxN-cross-bar-switch
Axis based MxN cross bar switch implementation
jomonkjoy/EthernetTimeSynchronizer
jomonkjoy/FFT-Computation
Fast Fourier Transform (FFT) algorithm computes the discrete Fourier transform (DFT) of a sequence, or its inverse (IFFT)
jomonkjoy/Matrix-Multiplication
Accelerator for Floating Point Matrix Multiplication
jomonkjoy/SDRAM-Controller
EDEC STANDARD Double Data Rate (DDR) SDRAM Specification
jomonkjoy/arty_ntp_client
NTP client for Arty-7 35T board
jomonkjoy/bladeRF-wiphy
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
jomonkjoy/corundum
Open source FPGA NIC
jomonkjoy/digital-flow
This is a tutorial on standard digital design flow
jomonkjoy/digital-fm-stereo-modulator
All-digital FM Stereo Modulator described in Verilog.
jomonkjoy/FIR-Filter
FIR Filter Add/Shift implementation using Inverted form
jomonkjoy/hdmi
Send video/audio over HDMI on an FPGA
jomonkjoy/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
jomonkjoy/Microsemi-SmartFusion2-Device
Synthesis optimized Design for Microsemi SmartFusion2 Device resources
jomonkjoy/openlane
OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
jomonkjoy/openwifi
open-source Wi-Fi baseband chip/FPGA design
jomonkjoy/p4fpga
P4-14/16 Bluespec Compiler
jomonkjoy/Perl-repo
jomonkjoy/Pixblasters-MicroDemo-APA102
FPGA Controller for APA102 and compatible RGB LEDs
jomonkjoy/Python-repo
jomonkjoy/riscv_software_build
Compiling C code for the RISC-V RV32I architecture using a linker script
jomonkjoy/SD-Card-sdk
jomonkjoy/systemc-2.3.3
SystemC 2.3.3 (Includes TLM)
jomonkjoy/Xilinx-7series-Design
Synthesis optimized Design for Xilinx 7 Series CLB resources