/AXIS-Async-FIFO

parameterized AXIS FIFO design

Primary LanguageVerilog

AXIS-Async-FIFO

parameterized AXIS FIFO design

Description:

         The top -level FIFO module is a parameterized FIFO design with all sub-blocks 
         instantiated using the recommended practice of doing named port connections.

Reference :

         Simulation and Synthesis Techniques for Asynchronous FIFO Design 
         Clifford E. Cummings, Sunburst Design, Inc. 
         cliffc@sunburst-design.com