jomonkjoy

jomonkjoy's Stars

• keon/algorithms

  Minimal examples of data structures and algorithms in Python

  Language:Python24.2k6351644.6k

• open-sdr/openwifi

  open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

  Language:C4k132346665

• intel/haxm

  Intel® Hardware Accelerated Execution Manager (Intel® HAXM)

  Language:C3.3k150287883

• lowRISC/opentitan

  OpenTitan: Open source silicon root of trust

  Language:SystemVerilog2.6k1066.9k792

• openhwgroup/cva6

  The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

  Language:Assembly2.3k931.1k705

• jbush001/NyuziProcessor

  GPGPU microprocessor architecture

  Language:C2k142168356

• lowRISC/ibex

  Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

  Language:SystemVerilog1.4k99838557

• The-OpenROAD-Project/OpenLane

  OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  Language:Python1.4k61963379

• alexforencich/verilog-pcie

  Verilog PCI express components

  Language:Verilog1.2k5251306

• chipsalliance/riscv-dv

  Random instruction generator for RISC-V processor verification

  Language:Python1k82351332

• verilog-to-routing/vtr-verilog-to-routing

  Verilog to Routing -- Open Source CAD Flow for FPGA Research

  Language:C++1k671k397

• openhwgroup/cv32e40p

  CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

  Language:SystemVerilog98382485428

• drom/awesome-hdl

  Hardware Description Languages

  982622097

• westerndigitalcorporation/swerv_eh1

  A directory of Western Digital’s RISC-V SweRV Cores

  Language:SystemVerilog859950132

• Xilinx/dma_ip_drivers

  Xilinx QDMA IP Drivers

  Language:C59348191427

• MicroCoreLabs/Projects

  Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8, MCL6809, XTMax

  Language:C++402362482

• bluespec/Flute

  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

  Language:Bluespec360221656

• grahamedgecombe/icicle

  32-bit RISC-V system on chip for iCE40 FPGAs

  Language:Python303261352

• agalimberti/NoCRouter

  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni

  Language:SystemVerilog1188137

• NetFPGA/P4-NetFPGA-public

  P4-NetFPGA wiki

  1031897431

• p4fpga/p4fpga

  P4-14/16 Bluespec Compiler

  Language:Bluespec83272326

• unixpunk/PlutoWeb

  PlutoWeb

  Language:JavaScript73105819

• archlabo/Frix

  IBM PC Compatible SoC for a commercially available FPGA board

  Language:Verilog6811210

• brianwchh/grassrootsstartup-ComputerVsion-zynq

  Language:C393012

• mattvenn/TinyFPGA-BX

  Language:AGS Script33403

• blackmesalabs/ChipVault

  Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.

  Language:Perl10100

• PixiGreen/Pixblasters-MicroDemo-APA102

  FPGA Controller for APA102 and compatible RGB LEDs

  Language:VHDL8101

• filipamator/arty_ntp_client

  NTP client for Arty-7 35T board

  Language:VHDL6205

• diocorreia/digital-fm-stereo-modulator

  All-digital FM Stereo Modulator described in Verilog.

  Language:Verilog2102

• tukl-msd/msdlib.vhdl

  VHDL helper library with generic components and helper functions

  Language:TeX2401