chipsalliance/riscv-dv

Issues

• [pygen] riscv_rand_instr_test run failed

  #947 opened a year ago by sky1989123
  1

• Can riscv-dv used with ucb rocket core/boom core?

  #979 opened 7 months ago by Sai-Manish
  6

• Error: unrecognized opcode `csrr x5,0xf14', extension `zicsr' required

  #968 opened a year ago by AhmedAmrAbdellatif1
  10

• Can't do S-mode test ( No delegation )

  #975 opened 8 months ago by AhmedAmrAbdellatif1
  3

• Understanding the Role of UVM and Circuit Simulators

  #990 opened 4 months ago by mutianzh
  0

• Error: illegal operands `sd s11,sub_4_stack_p(s5)'

  #986 opened 6 months ago by il-steffen
  0

• riscv-dv breaks with riscv64-unknown-elf-gcc version tags 2023.04.18 and up

  #964 opened a year ago by 5hayanB
  5

• Can I run this without install any external library?

  #982 opened 6 months ago by kjhhgt76
  0

• Error "SolveBeforeMustBeRand" while Elaborating with Dsim tool

  #967 opened a year ago by magnetworks
  2

• Request for detailed documentation

  #978 opened 7 months ago by fangzhigang32
  1

• can't do riscv_csr_test

  #972 opened 10 months ago by AhmedAmrAbdellatif1
  1

• Initial mret (from init_supervisor_mode) sends processor to untranslated address

  #977 opened 8 months ago by talhashahzad12345
  0

• Randomize CSR in main

  #976 opened 8 months ago by predator-111
  6

• Guide lines to enable virtual address translation?

  #974 opened 9 months ago by mukesh891
  0

• How to test Atomic Extension?

  #973 opened 9 months ago by AhmedAmrAbdellatif1
  3

• Access Exception error while running spike for rv64imac instructions

  #971 opened 10 months ago by omanzoor
  0

• Error: illegal operands `sd s11,sub_4_stack_p(s5)'

  #969 opened 10 months ago by AhmedAmrAbdellatif1
  0

• How to connect the test to my SV design file, and How do I get the feedback that the test has passed or failed?

  #970 opened a year ago by AhmedAmrAbdellatif1
  1

• Circular dependency within source files

  #966 opened a year ago by yesilzeytin
  0

• spike error：free(): invalid pointer: 0xxxxxxx

  #965 opened a year ago by Lebattt
  0

• rv64gc failing spike due to exception trap_store_address_misaligned

  #963 opened a year ago by kevinhe5
  2

• Test cases generated for riscv64gc target do not run on latest version of spike

  #937 opened 2 years ago by KatCe
  10

• The spike simulation gets stuck in an endless loop

  #962 opened a year ago by riscv1111
  2

• Can not find file `VECTOR_INCLUDE("riscv_instr_cover_group_inc_cg_sample.sv") etc file path

  #938 opened a year ago by lchuwen
  1

• use ovpsim .Why is there no verbose log instruction

  #958 opened a year ago by moyouth
  5

• spike

  #961 opened a year ago by riscv1111
  0

• Instruction Address Misalign Exception

  #957 opened a year ago by bmverma
  0

• for debug mode, how to modify link.ld to match debug rom enter addr

  #951 opened a year ago by Van2Jo
  1

• for debug mode, how to modify link.ld to match debug rom enter addr

  #952 opened a year ago by Van2Jo
  0

• for debug mode, how to modify link.ld to match debug rom enter addr

  #953 opened a year ago by Van2Jo
  0

• for debug mode, how to modify link.ld to match debug rom enter addr

  #954 opened a year ago by Van2Jo
  0

• mmode_exception_handler is not considering the instruction misaligned, load address misaligned, store/amo address misaligned

  #949 opened a year ago by annasaikiran
  0

• how to generate compressed instructions regression test

  #945 opened a year ago by GMYMingyu
  3

• pyflow callstack_gen randomize fail

  #946 opened a year ago by sky1989123
  1

• Test generation failed for riscv_amo_test

  #944 opened a year ago by jayasree2411
  0

• no_load_store switching option

  #943 opened a year ago by hyperion009
  0

• RVC Instruction gpr coverage collection omissions for CR/CI/CSS formate

  #942 opened a year ago by LongStudy
  0

• riscv_csr_test fails at generation

  #941 opened a year ago by fraret
  0

• use pyflow error: ModuleNotFoundError: No module named 'ucis.ucdb'

  #940 opened a year ago by Damien-Wu
  1

• pygen requirements installation failure

  #934 opened 2 years ago by ElectronicBatman
  4

• WRITE_GPR in gen_signature_handshake() produces invalid assembly

  #939 opened a year ago by serge0699
  0

• SEW=16 vfcvt/vfwcvt instruction

  #933 opened 2 years ago by chLZX
  0

• FLW uses rs1 as integer base ISA

  #936 opened 2 years ago by dd-baoshan
  0

• vfwcvt.xu.f.v issue

  #932 opened 2 years ago by chLZX
  0

• CRITICAL Cannot randomize branch target instruction

  #928 opened 2 years ago by thewesley77
  1

• kIllegalCompressedOpcode generates valid instruction (```c.fswsp```) when XLEN=32

  #927 opened 2 years ago by atsushi-shinbo-esoltrinity
  1

• [page table] There is a error in page table !

  #926 opened 2 years ago by EdisonChenxiansheng
  0

• [cfg,gpr] reg constraint in riscv_gen_config.

  #922 opened 2 years ago by SerLippo
  1

• Spike Log to Trace csv is skipping floating Point Instructions which are editing status registers

  #919 opened 2 years ago by qaziullah
  0

• Is the coverage model I generated broken when I run ‘cov' command?

  #918 opened 2 years ago by Zhengshuhang
  0