chipsalliance/riscv-dv

FLW uses rs1 as integer base ISA

dd-baoshan opened this issue · 0 comments

dd-baoshan commented

Floating-point load use the base+offset addressing mode as the integer base ISA, with a base address in register rs1 ad a 12-bit signed byte offset.
We need to set has_rs1 at following file for load instruction.

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