alexforencich/verilog-pcie

Issues

• why 'loading out-of-tree module taints kernel.' and 'example: module verification failed: signature and/or required key missing - tainting kernel'

  #56 opened a month ago by Jaegerseki
  1

• Whether PCIe Gen4/Gen5 is supported？

  #55 opened 2 months ago by Jzone315
  2

• Driver and Verilog mismatch

  #52 opened 3 months ago by alexisfrjp
  4

• Why is test data mismatching in example_driver

  #54 opened 3 months ago by francoccc
  3

• dma + axi memory

  #53 opened 3 months ago by juanma-rm
  0

• Implementation of the TL and DL functions of the PCIE protocol

  #51 opened 4 months ago by KavinGarnet
  1

• why I run the test instance of tb , it report cannot import module dma_ram?

  #50 opened 4 months ago by zhfff4869
  2

• python report the error about the path in dma_psdp_ram.py , why?

  #49 opened 4 months ago by zhfff4869
  1

• make:No rule to make target

  #48 opened 6 months ago by Jaegerseki
  0

• request for pcie axi slave verilog

  #47 opened 6 months ago by vpsampath123
  1

• Segmented memory address bug caused by ram_mask_1_reg assertion in dma_if_pcie_rd.v

  #46 opened 7 months ago by C0L
  0

• FPGA versus FPGA_AXI Example Questions

  #31 opened 2 years ago by softerhardware
  10

• Which part is the digital part of Serdes Phy?

  #45 opened 7 months ago by myqlee
  2

• Standalone use

  #44 opened 8 months ago by jamesoncollins
  2

• I have two questions ,can someone help me

  #43 opened 8 months ago by hdu-lpl
  1

• Using both DMA and separate AXI Slave as PCIe requester?

  #40 opened a year ago by dbarrie
  2

• AXI dma client support?

  #37 opened a year ago by chenbo-again
  1

• Implementation of PCIe “Non-Transparent Bridge" (NTB)

  #39 opened a year ago by ohault
  2

• What name of the Top module name of all the verilogs in rtl folder?

  #38 opened a year ago by asifikbal827
  1

• About pcie_us_if

  #34 opened a year ago by GGbang2
  1

• bug in dma_if_pcie_rd when max read request size is set to 4096 bytes

  #35 opened a year ago by EricCSun
  0

• Why there is no sgDMA in example_core.v

  #33 opened a year ago by chenbo-again
  3

• dma_read_desc_status_valid not asserted when requesting memory read length > 8

  #24 opened 3 years ago by filamoon
  9

• How to test pcie_us_axi_dma on board?

  #32 opened 2 years ago by hardikvala
  0

• Add P-tile support

  #12 opened 2 years ago by alexforencich
  1

• Intel PCIe IP model

  #2 opened 5 years ago by bluecmd
  3

• Send immediate data to host?

  #27 opened 2 years ago by filamoon
  4

• what is the purpose of ram_wr_done and how to assert it?

  #23 opened 2 years ago by filamoon
  1

• Doc?

  #30 opened 2 years ago by hughperkins
  1

• typo in Stratix 10 shim

  #29 opened 2 years ago by EricCSun
  2

• unexpected dma read request logged

  #28 opened 2 years ago by filamoon
  3

• Support of CXL 2.0

  #25 opened 3 years ago by ohault
  0

• Support for Xilinx soft PCIe PHY?

  #22 opened 3 years ago by Elgox2
  1

• Communication between logic and host using PCIe

  #21 opened 3 years ago by minlno
  7

• 64bit write/read instead of 32bit

  #18 opened 3 years ago by chauhanjoy
  5

• Add Stratix 10 GX/MX device support

  #15 opened 3 years ago by alexforencich
  1

• cocotb installaion commands

  #17 opened 3 years ago by chauhanjoy
  0

• Is there a driver for window7/10？

  #16 opened 3 years ago by dreamchenhao
  2

• Module not found issue comming

  #14 opened 3 years ago by chauhanjoy
  3

• Add Arria 10 device support

  #11 opened 4 years ago by alexforencich
  0

• Add support for adm-pcie-8v3

  #13 opened 4 years ago by Applepi
  0

• vivado version

  #7 opened 4 years ago by shahbaazlokh
  10

• Request for U200 Support

  #8 opened 4 years ago by CGavinMullis
  5

• AU50 example fails to generate bitstream

  #9 opened 4 years ago by TaekyungHeo
  2

• Example host code on top of the kernel module?

  #6 opened 5 years ago by FPGA-Bot-Yang
  24

• Make failure for example VU1525/fpga_axi/driver

  #5 opened 5 years ago by FPGA-Bot-Yang
  7

• pcie_disable_fatal_err.sh not working

  #3 opened 5 years ago by yakirgb
  12

• Package tb/pcie.py as a pip package

  #4 opened 5 years ago by bluecmd
  4

• Hope to support xilinx kc705 pcie2.0

  #1 opened 5 years ago by hushunkui
  1