Issues
- 1
why 'loading out-of-tree module taints kernel.' and 'example: module verification failed: signature and/or required key missing - tainting kernel'
#56 opened by Jaegerseki - 2
Whether PCIe Gen4/Gen5 is supported?
#55 opened by Jzone315 - 4
Driver and Verilog mismatch
#52 opened by alexisfrjp - 3
Why is test data mismatching in example_driver
#54 opened by francoccc - 0
dma + axi memory
#53 opened by juanma-rm - 1
- 2
- 1
- 0
make:No rule to make target
#48 opened by Jaegerseki - 1
request for pcie axi slave verilog
#47 opened by vpsampath123 - 0
Segmented memory address bug caused by ram_mask_1_reg assertion in dma_if_pcie_rd.v
#46 opened by C0L - 10
FPGA versus FPGA_AXI Example Questions
#31 opened by softerhardware - 2
Which part is the digital part of Serdes Phy?
#45 opened by myqlee - 2
Standalone use
#44 opened by jamesoncollins - 1
I have two questions ,can someone help me
#43 opened by hdu-lpl - 2
- 1
AXI dma client support?
#37 opened by chenbo-again - 2
Implementation of PCIe “Non-Transparent Bridge" (NTB)
#39 opened by ohault - 1
- 1
About pcie_us_if
#34 opened by GGbang2 - 0
- 3
Why there is no sgDMA in example_core.v
#33 opened by chenbo-again - 9
dma_read_desc_status_valid not asserted when requesting memory read length > 8
#24 opened by filamoon - 0
How to test pcie_us_axi_dma on board?
#32 opened by hardikvala - 1
Add P-tile support
#12 opened by alexforencich - 3
Intel PCIe IP model
#2 opened by bluecmd - 4
Send immediate data to host?
#27 opened by filamoon - 1
- 1
Doc?
#30 opened by hughperkins - 2
typo in Stratix 10 shim
#29 opened by EricCSun - 3
unexpected dma read request logged
#28 opened by filamoon - 0
Support of CXL 2.0
#25 opened by ohault - 1
Support for Xilinx soft PCIe PHY?
#22 opened by Elgox2 - 7
Communication between logic and host using PCIe
#21 opened by minlno - 5
64bit write/read instead of 32bit
#18 opened by chauhanjoy - 1
Add Stratix 10 GX/MX device support
#15 opened by alexforencich - 0
cocotb installaion commands
#17 opened by chauhanjoy - 2
Is there a driver for window7/10?
#16 opened by dreamchenhao - 3
Module not found issue comming
#14 opened by chauhanjoy - 0
Add Arria 10 device support
#11 opened by alexforencich - 0
Add support for adm-pcie-8v3
#13 opened by Applepi - 10
vivado version
#7 opened by shahbaazlokh - 5
Request for U200 Support
#8 opened by CGavinMullis - 2
AU50 example fails to generate bitstream
#9 opened by TaekyungHeo - 24
- 7
- 12
pcie_disable_fatal_err.sh not working
#3 opened by yakirgb - 4
Package tb/pcie.py as a pip package
#4 opened by bluecmd - 1
Hope to support xilinx kc705 pcie2.0
#1 opened by hushunkui