Pinned Repositories
AcornHDMI
DVI/HDMI buffer for SQRL Acorn Artix-7 FPGA board
ads1-notebooks
Copies of notebooks used in the practical sessions for Algorithms for DNA Sequencing
artix-dc-scm
Experimental Xilinx Artix-7 driven Data Center Security Communication Module
Ethash-C-Implementation
C implementation of Ethash algorithm
Picoevb_Keccak256hash_Pcie_ipi
Keccak256 hash on picoevb fpga pcie board with xilinx artix7 FPGA
X13-Hash-Test
Library to test c++ X13 hash
xilinx-ethash
Run ethash opencl kernel on Xilinx's Alveo U50
xmr-miner
Monero (v11 updated) miner with remote configuration file (eg. pastebin raw file) supported
shahbaazlokh's Repositories
shahbaazlokh/Picoevb_Keccak256hash_Pcie_ipi
Keccak256 hash on picoevb fpga pcie board with xilinx artix7 FPGA
shahbaazlokh/xmr-miner
Monero (v11 updated) miner with remote configuration file (eg. pastebin raw file) supported
shahbaazlokh/Ethash-C-Implementation
C implementation of Ethash algorithm
shahbaazlokh/xilinx-ethash
Run ethash opencl kernel on Xilinx's Alveo U50
shahbaazlokh/AcornHDMI
DVI/HDMI buffer for SQRL Acorn Artix-7 FPGA board
shahbaazlokh/artix-dc-scm
Experimental Xilinx Artix-7 driven Data Center Security Communication Module
shahbaazlokh/astor-network
Ethereum.org Website 2019 Redesign
shahbaazlokh/axi4_master
Custom axi4 master
shahbaazlokh/CryptoStreams
Tool for generation of data from cryptoprimitives (block and stream ciphers, hash functions). Cryptoprimitives are round-reduced and the data can be configured for multiple testing scenarios.
shahbaazlokh/Custom_Part_Data_Files
Xilinx PCIe to MIG DDR4 example designs and custom part data files
shahbaazlokh/daggen
Generate ethereum DAG with special block number.
shahbaazlokh/eaglesong
shahbaazlokh/eaglesong_hash
shahbaazlokh/eaglesong_python
eaglesong C hash library for python. with CKB
shahbaazlokh/EmbeddedLinuxBBB
shahbaazlokh/ethash
shahbaazlokh/FPGA-Keccak-Miner
shahbaazlokh/loadcell_stm32f0
loadcell with STM32f0 and oled display with pc design and application code
shahbaazlokh/NexysPsram
AXI PSRAM Controller IP for use with Digilent Nexys 4
shahbaazlokh/NXS-FPGA
NXS FPGA Verilog
shahbaazlokh/Open-CryptoNight-ASIC
Open source hardware implementation of classic CryptoNight
shahbaazlokh/OpenCL-101
Learn OpenCL step by step.
shahbaazlokh/SQRL_FK33
SQRL FK33 board files, example designs and scripts.
shahbaazlokh/SQRL_FK33_SDAccel
shahbaazlokh/UART_Artix7_FPGA_Verilog_RTL
This is project is intended to send "hello" from fpga to host, uart core module runs at 50MHz, with the baudrate of 9600,
shahbaazlokh/vcu1525_scripts
Various VCU/BCU/BTU scripts and tools.
shahbaazlokh/Vitis-HLS-Introductory-Examples
shahbaazlokh/vsdflow
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
shahbaazlokh/x16r_hash
Python module for x16r hash function
shahbaazlokh/x21s_hash