alexforencich/verilog-pcie

I have two questions ,can someone help me

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Hello, I am a beginner. I want to use these open source module to build a module similar to xilinx's XDMA IP function. Regarding the pcie_axi_master module, I saw the explanation you gave is :It can be used to terminate device-to-device DMA operations with reasonable performance.I don't understand what this terminate means.can you help me ?And How can I use these modules to combine into a function similar to XDMA? I am just learning it as an individual and do not need to use it for other purposes.

PCIe devices can assume roles of requester/initiator/bus master or completer/target. Requesters initiate memory read/write operations, and completers terminate read/write operations, potentially generating a completion which is returned to the requester. The CPU is always a requester (load and store operations initiate memory reads and writes), and the memory controller is always a completer (memory reads and writes are terminated by, well, reading and writing system memory). Other devices on the bus can take on both roles as appropriate - they can initiate DMA operations, or terminate operations on their BARs that were initiated by other devices. So, the DMA interface module serves in the requester/initiator role (generating read/write operations against system memory and/or other devices in the hierarchy), and the PCIe AXI master module serves in the completer/target role (terminating read/write operations that were initiated by other devices).