SystemRDL/PeakRDL-uvm

Issues

• Feature: Generate covergroup for accesses to registers

  #34 opened a month ago by quoll99
  0

• Backdoor access by better use of configure() or add_hdl_path()

  #33 opened 3 months ago by paul-demo
  0

• Feature: option to replace the base class of generated registers

  #31 opened 4 months ago by Furetur
  1

• generate verilog file, not system verilog.

  #30 opened 10 months ago by yqdvan
  2

• Clear Namespace DB on subsequent exports.

  #28 opened 10 months ago by hughjackson
  0

• [v3.0] During export, check for identifier collisions in output

  #26 opened a year ago by amykyta3
  0

• Contribution to PeakRDL uvm and pdf

  #16 opened a year ago by muneebullashariff
  3

• [feature request] Add user_template_dir to config

  #24 opened a year ago by Dragon-Git
  0

• [v3.0] Improve user-extensibility of generated UVM code

  #17 opened 2 years ago by amykyta3
  0

• [v3.0] Add support for donttest/doncompare

  #23 opened a year ago by amykyta3
  0

• default hdl_path support

  #22 opened 2 years ago by hughjackson
  3

• [v3.0] Refactor to align better with official UVM 1.2 user guide

  #21 opened 2 years ago by amykyta3
  0

• [v3.0] Add better support for vertical re-use of UVM register models

  #20 opened 2 years ago by amykyta3
  0

• [v3.0] Add better user control for when virtual registers are used

  #19 opened 2 years ago by amykyta3
  0

• [v3.0] Add identifier filter

  #18 opened 2 years ago by amykyta3
  0

• [v3.0] hdl_path property does not work with regard to addrmap and regfile components

  #13 opened 3 years ago by eeeeewwz
  2

• Announcement: Deprecating import via "peakrdl.uvm" namespace package

  #14 opened 2 years ago by amykyta3
  0

• hello，dear ，the systemrdl have keyword msb0，lsb0；i add msb0 to my rdl ，but it do not work，the fields bits sequence not change ，hwo to solve the problem？

  #15 opened 2 years ago by jiangqingliu88
  2

• Implement has_reset property of fields

  #12 opened 3 years ago by mpriestleyidex
  2

• mem access type typo

  #11 opened 3 years ago by mpriestleyidex
  1

• Type name is not uniquified if parameter from parent scope is used

  #10 opened 4 years ago by hughjackson
  3

• hdl_path_slice implementation

  #8 opened 4 years ago by soleshka
  2

• uvm_reg_fifo based on rdl

  #7 opened 4 years ago by soleshka
  1

• Announcement: Renaming 'RALBot-uvm' to 'PeakRDL-uvm'

  #4 opened 4 years ago by amykyta3
  0

• Print the UVM RAL data, with MSB bits first

  #6 opened 4 years ago by muneebullashariff
  1

• Is this project supported ?

  #2 opened 5 years ago by aveerubhotla-ventana
  1

• Continue work on SystemRDL/RALBot-uvm instead of here

  #1 opened 5 years ago by amykyta3
  6