Pinned Repositories
abc
ABC: System for Sequential Logic Synthesis and Formal Verification
bsg_fakeram
fakeram generator for use by researchers who do not have access to commercial ram generators
FakeRAM2.0
IHP-Open-PDK
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
OpenROAD-flow-scripts
OpenSTA
pyslang
Python bindings for slang, a library for compiling SystemVerilog
siliconcompiler
A modular build system for hardware
slang
SystemVerilog compiler and language services
gadfort's Repositories
gadfort/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
gadfort/abc
ABC: System for Sequential Logic Synthesis and Formal Verification
gadfort/bsg_fakeram
fakeram generator for use by researchers who do not have access to commercial ram generators
gadfort/FakeRAM2.0
gadfort/IHP-Open-PDK
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
gadfort/OpenROAD-flow-scripts
gadfort/OpenSTA
gadfort/pyslang
Python bindings for slang, a library for compiling SystemVerilog
gadfort/siliconcompiler
A modular build system for hardware
gadfort/slang
SystemVerilog compiler and language services
gadfort/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
gadfort/tf_import
Reads a Cadence techfile into KLayout and produces layer properties from it
gadfort/yosys
Yosys Open SYnthesis Suite