Pinned Repositories
Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
abseil-cpp
Abseil Common Libraries (C++)
Cores-SweRV
SweRV EH1 core
float-toy
Use this to build intuition for the IEEE floating-point format
simview
Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
verilator
Verilator open-source SystemVerilog simulator and lint system
verilator
Verilator open-source SystemVerilog simulator and lint system
wxWidgets
Cross-Platform C++ GUI Library
pieter3d's Repositories
pieter3d/simview
pieter3d/abseil-cpp
Abseil Common Libraries (C++)
pieter3d/Cores-SweRV
SweRV EH1 core
pieter3d/float-toy
Use this to build intuition for the IEEE floating-point format
pieter3d/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
pieter3d/UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
pieter3d/verilator
Verilator open-source SystemVerilog simulator and lint system