chipsalliance/riscv-vector-tests

Issues

• VLEN 2048 tests size

  #40 opened 7 months ago by FariaaFaheem
  2

• Instructions which read at 2xSEW should be initialized with 2xSEW

  #32 opened 9 months ago by jerryz123
  0

• Test vsetvli with x0 source operand

  #33 opened 9 months ago by jerryz123
  0

• Use tail/mask undisturbed instead of agnostic

  #35 opened 9 months ago by troibe
  6

• Need more test case for vector index load/store

  #12 opened 9 months ago by huxuan0307
  7

• Add tests for vlseg<nf>e<eew>ff.v

  #39 opened 9 months ago by troibe
  2

• for VLEN=2048 test script gives errors.

  #37 opened 9 months ago by akifejaz
  12

• Custom tests generation

  #36 opened 9 months ago by akifejaz
  1

• Tests for vsext.vf4/8 and vzext.vf4/8 rely on inital values of vector registers

  #26 opened a year ago by troibe
  1

• Add more tests which check CSR functionality

  #21 opened a year ago by troibe
  8

• Check vxsat setting

  #20 opened a year ago by jerryz123
  2

• Test all cases of VXRM.

  #19 opened a year ago by jerryz123
  2

• Restrict virtual mode tests to vector load/store only?

  #17 opened a year ago by jerryz123
  2

• Make for target 'build-patcher-spike' failed

  #18 opened a year ago by ptzheng
  10

• Restrict virtual mode tests to vector load/store only?

  #16 opened a year ago by jerryz123
  1

• How to use this project for plct-gem5？

  #15 opened a year ago by luojihe
  5

• Store tests seem to check wrong address

  #11 opened a year ago by jerryz123
  7

• Store tests should check memory regions touched by store.

  #10 opened a year ago by jerryz123
  1