Nic30/hdlConvertor

Issues

• Prebuilt Binary Release to PyPi

  #187 opened a year ago by khwong-c
  12

• meson build fails, unable to find <hdlConvertor/verilogPreproc/verilogPreprocParser/verilogPreprocLexer.h>

  #193 opened 6 months ago by crsumiran
  4

• incorrect Position

  #166 opened 3 years ago by Thomasb81
  6

• Preprocessor - expose complete parser?

  #165 opened 3 years ago by the-moog
  12

• Error in CMake based build

  #190 opened 8 months ago by Siddhartha123
  2

• VHDL components are incorectly rewritten from HDL AST back to VHDL

  #189 opened 9 months ago by skedzierski
  0

• Error when preprocessing verilog header with dos line endings

  #180 opened a year ago by nxpMartin
  5

• CMake install DIRECTORY include wrong parameters?

  #182 opened 2 years ago by liuzikai
  2

• Dockerfile is outdated

  #184 opened a year ago by KatCe
  4

• Can't build master on ubuntu 22.04

  #183 opened a year ago by poleguy
  6

• (System)Verilog parallel_case attribute is not supported

  #185 opened a year ago by KatCe
  1

• Convert VHDL package to Verilog or SV

  #168 opened 3 years ago by jabate-anova
  2

• Build error on windows

  #179 opened 2 years ago by TitanCheat
  2

• Using updated SV/Verilog, VHDL Grammars

  #178 opened 2 years ago by AmeyaVS
  2

• Question regarding VHDL to hwt

  #164 opened 2 years ago by kaidoho
  4

• `Conversion to Python object not implemented` Error from Primitive Structural Verilog Code

  #173 opened 2 years ago by TheMatt2
  3

• Updating Git Submodules For Tests

  #177 opened 2 years ago by AmeyaVS
  1

• ANTLR 4.11.1 support

  #171 opened 2 years ago by apatern0
  2

• provided instructions don't work for finding antlr-complete.jar

  #172 opened 2 years ago by bsferrazza
  6

• KeyError when working with ternary operators and ranges?

  #170 opened 3 years ago by shafe123
  3

• Verilog2017 - unpacked array converted as packed

  #169 opened 3 years ago by diffore
  2

• Handling extraneous commas (SystemVerilog)

  #163 opened 3 years ago by the-moog
  1

• Replace scikit-build/cmake with mesonpep517/meson (potential drop of python2.7 support)

  #162 opened 3 years ago by Nic30
  1

• SV grammar hirarchical identifier in delay_value rule

  #160 opened 3 years ago by Thomasb81
  0

• Test std2017_p333 has incorrect syntax

  #159 opened 3 years ago by jrudess
  1

• Shared Variables within VHDL not implemented?

  #158 opened 4 years ago by hjnauman
  7

• Value attribute missing from HdlIdDef objects when declared on the same line.

  #157 opened 4 years ago by hjnauman
  1

• NotImplementedError: Unexpected object of type Error,

  #151 opened 4 years ago by SingaDK
  4

• VHDL: Functions with no arguments are not handled correctly when trying to write AST to VHDL

  #155 opened 4 years ago by Partidani
  4

• VHDL: open is not handled correctly when trying to write AST to VHDL

  #154 opened 4 years ago by Partidani
  1

• VHDL: direct instantiation is not handled correctly when trying to write AST to VHDL

  #153 opened 4 years ago by Partidani
  1

• VHDL: exit statements are not handled in the HDL AST

  #152 opened 4 years ago by Partidani
  1

• SystemVerilog import package - doesn't seem to do anything?

  #149 opened 4 years ago by flemish4
  8

• VHDL: cannot visit NULL statement

  #147 opened 4 years ago by andrasm62
  2

• VHDL: cannot visit FOR LOOP within a function

  #146 opened 4 years ago by andrasm62
  5

• VHDL: proper tests for comment parsing

  #148 opened 4 years ago by Nic30
  0

• Visual Studio 2019 x64 exit code -1073741571 (probably memory leak)

  #143 opened 4 years ago by Nic30
  1

• Can the normal mode and the preprocessing mode SystemVerilog Grammar be combined into one file?

  #144 opened 4 years ago by itviewer
  5

• hdlConvertor._hdlConvertor.ParseException: test.v:90:1:Error: protect is not defined

  #129 opened 4 years ago by lionheart117
  16

• VHDL: Slicing and range attributes incorrectly identified as function calls.

  #140 opened 4 years ago by mewais
  13

• VHDL: Arrays of unbounded elements not working correctly.

  #141 opened 4 years ago by mewais
  0

• physical_type_definition representation in HDL AST

  #138 opened 4 years ago by Nic30
  4

• Package Instantiation in VHDL

  #136 opened 4 years ago by mewais
  2

• Add file name to CodePosition

  #134 opened 4 years ago by tictacmenthe
  5

• ModuleParser.module_item.generate_region Conversion to Python object not implemented

  #122 opened 4 years ago by lionheart117
  18

• VHDL syntax error with `end generate` keyword

  #133 opened 4 years ago by mewais
  4

• BLIF support

  #132 opened 4 years ago by mewais
  7

• notebooks with examples

  #131 opened 5 years ago by Nic30
  0

• New release 1.6 discussion.

  #123 opened 5 years ago by Nic30
  7

• An import error for hdlConvertor/tests/test_verilog_conversion.py

  #124 opened 5 years ago by lionheart117
  1