tictacmenthe

Embedded Systems Engineering, specialized in FPGAs, France. High interest in Electronics, Embedded Software Engineering, FPGAs, and Machine Learning.

@outech-robotic France

Pinned Repositories

verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
Language:C++1.3k 50 929197
rplidar_a2
RPLidar A2 C++ library
Language:C++6 6 02
code
All the software used for our robots for the French Robotics Cup
Language:C8 6 322
dotfiles
Language:Shell00
F2CNN
Speech feature extraction using Gammatone FilterBank and CNN
Language:Python32
LidarVisualisation
Visualisation des données des lidars avec ou sans traitement obstacles
Language:CMake00
outech-code
All the software used for our robots for the French Robotics Cup
Language:C00
outech-replay
Replay robot simulations using HTML5 canvas
Language:JavaScript00
RPU
Basic RISC-V CPU implementation in VHDL.
Language:VHDL00
TasteSomePizza
TSP's Tower Defence
Language:Java00

tictacmenthe's Repositories

tictacmenthe/F2CNN
Speech feature extraction using Gammatone FilterBank and CNN
Language:Python32
tictacmenthe/dotfiles
Language:Shell00
tictacmenthe/LidarVisualisation
Visualisation des données des lidars avec ou sans traitement obstacles
Language:CMake00
tictacmenthe/outech-code
All the software used for our robots for the French Robotics Cup
Language:C00
tictacmenthe/outech-replay
Replay robot simulations using HTML5 canvas
Language:JavaScript00
tictacmenthe/RPU
Basic RISC-V CPU implementation in VHDL.
Language:VHDL00
tictacmenthe/TasteSomePizza
TSP's Tower Defence
Language:Java00