veripool/verilog-mode

Issues

• Support bind outside module with AUTOINST and verilog-auto-star-expand

  #1888 opened a month ago by padams-manc
  1

• Accumulate bus width automatically

  #1887 opened a month ago by Nianuu
  3

• verilog-warn-fatal ignored in batch mode

  #1886 opened 2 months ago by techdude
  1

• Support for Verilog co-pilot or code asssitant in emacs

  #1885 opened 2 months ago by engrvns
  1

• SystemVerilog attributes in module declaration are getting modified when expanding AUTOs

  #1884 opened 2 months ago by cswmeta
  4

• Unable to set font-lock-punctuation-face color

  #1882 opened 4 months ago by sonofthesand
  1

• another question for replace port parameters

  #1881 opened 4 months ago by huabaoo
  2

• instance ports order is not as delclaration order after set verilog-auto-inst-sort as nil

  #1880 opened 7 months ago by WoodsLee1001
  1

• autowire generate wrong signal width

  #1879 opened 7 months ago by younghe1988
  1

• how to get the rest part of instance name?

  #1878 opened 8 months ago by zhanjf
  1

• For .sv files, verilog-mode cannot be recognized in Vim

  #1872 opened 8 months ago by 1371906755
  2

• Automatic Port Declaration Sorting in verilog-mode Tool

  #1876 opened 8 months ago by 1371906755
  1

• How to except multiple types in recognization (verilog-typedef-regexp)

  #1875 opened 8 months ago by szkarn
  2

• Emacs 29: Verilog Mode Font Hilighting: module keyword highlights following label in a comment block.

  #1874 opened 9 months ago by dspain55
  2

• When running xemacs -batch filename -f verilog-batch-auto from command line, I would like the results to have spaces instead of tabs

  #1873 opened 9 months ago by longhorngeek
  1

• This example( \(.*\) ) will result in an error

  #1870 opened 10 months ago by 1371906755
  13

• Installation problem

  #1871 opened 10 months ago by 1371906755
  1

• The regular expression .\(.*\) will result in an error if used alone.

  #1869 opened 10 months ago by 1371906755
  6

• parameter included in port list when is of user defined type

  #1868 opened 10 months ago by lucgozu
  1

• Port alignment issues

  #1867 opened 10 months ago by ramyamohandoss
  1

• FAQ not displaying correctly on github

  #1866 opened 10 months ago by bcrules82
  1

• Is there a way to align ports with /*AUTOINST*/ instead of the open parenthesis?

  #1865 opened 10 months ago by cswmeta
  1

• import packages not working in emacs.

  #1864 opened a year ago by deepak00agarwal
  1

• Word select in search stop at underscore

  #1863 opened a year ago by Diramu
  3

• Slow with many curly braces (`{`)

  #1860 opened a year ago by richyliu
  1

• indentation problem when there is a signal named "module_something"

  #1861 opened a year ago by rlarv
  1

• Port Coercion Issue on AUTOINPUT

  #1859 opened a year ago by ramyamohandoss
  7

• Remove xemacs requirement to build verilog-mode?

  #1858 opened a year ago by Pinjontall94
  2

• Typedef struct signals can't be AUTOINPUT(AUTOOUTPUT) generated when AUTOINST

  #1857 opened a year ago by lucychole
  1

• "package_name::type_t" typed AUTOINST ports do not generate/punch top module ports

  #1856 opened a year ago by marcink
  3

• autowire/logic on Concatenation operators apostrophe

  #1854 opened a year ago by anythingelse0
  2

• how to omit more port when autoinst by regex

  #1853 opened a year ago by zhanjf
  2

• AUTOLOGIC not decting correct size of multidimension arrays

  #1852 opened a year ago by amd013
  1

• typedefs in autooutput

  #1851 opened a year ago by amd013
  2

• Multi-Dimensional array template magic [][] substitution fails when original port name matches parent port name, and verilog-auto-inst-vector is off

  #1848 opened a year ago by techdude
  3

• Do you think it over mixed use with vhdl？

  #1849 opened a year ago by e665107
  1

• Using AUTOs with parameterized type

  #1847 opened a year ago by cswmeta
  2

• How to modify the distance/space/indent of the declaration in the AUTOINPUT/AUTOOUTPUT ？

  #1846 opened a year ago by szkarn
  12

• make test - fails with message

  #1845 opened a year ago by nipmac
  1

• Fix indention for restrict_property_statement

  #1836 opened a year ago by pbing
  3

• Wrong auto extremes computation when signal is connected to input and output

  #1844 opened a year ago by boorbajones
  4

• Remove the modport of the interface from AUTOINST

  #1842 opened a year ago by szkarn
  5

• Annotations in the AUTO_TEMPLATE

  #1843 opened a year ago by szkarn
  1

• How to align the parenthesis generated by autoinst?

  #1841 opened a year ago by zheBytedance
  2

• Issue when using `\` followed by `"`

  #1831 opened 2 years ago by LapinFou
  3

• RFE: option to have AUTORESET reset flops to `x` rather than `0`

  #1839 opened a year ago by jwise
  1

• Fix indention for cover_sequence_statement

  #1837 opened a year ago by pbing
  2

• How to make verilog mode not add output for internal signals?

  #1835 opened a year ago by bharanr
  3

• It there a way to align code inside assigns like follow?

  #1834 opened a year ago by LeoGitHuber
  1

• Comments added in template can be forwarded to the instantiation?

  #1832 opened 2 years ago by rahulrbharadwaj
  1