Pinned Repositories
fpga-hdl
A set of small Verilog projects, to simulate and implement on FPGA development boards
fri-magisterij
LaTeX templates for theses written at Faculty of Computer and Information Science, University of Ljubljana.
HDLDB
GDB server stub for replaying recorded HDL simulations
preimages-2D
2D cellular automata preimages count&list algorithm
rp32
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
soc-kit
System on Chip toolkit (Verilog 2001)
sockit_cdc
clock domain crossing FIFO
sockit_owm
SocKit 1-wire (onewire) master
SystemC-UVM
UVM-SystemC Library
TCB
Tightly Coupled Bus, low complexity, high performance system bus.
jeras's Repositories
jeras/sockit_owm
SocKit 1-wire (onewire) master
jeras/fpga-hdl
A set of small Verilog projects, to simulate and implement on FPGA development boards
jeras/rp8
RISC processor 8bit (AVR ISA), RTL based on 'navre'
jeras/sockit_cdc
clock domain crossing FIFO
jeras/butterflylogic
jeras/preimages-2D
2D cellular automata preimages count&list algorithm
jeras/SystemVerilog-tests
Tests for a set of SystemVerilog features over a set of simulation and synthesis tools.
jeras/verilog_coding_style
Verilog coding style examples
jeras/ivtest
Regression test suite for Icarus Verilog.
jeras/office
LibreOffice templates
jeras/sigrok
sigrok
jeras/sigrok-dump
Example sigrok dumps
jeras/sockit_i2c
I2C master/slave RTL and bench model code
jeras/webgl-quad-ca
WebGL QUAD CA sumulator
jeras/fri-magisterij
LaTeX templates for theses written at Faculty of Computer and Information Science, University of Ljubljana.
jeras/axi-bfm
Automatically exported from code.google.com/p/axi-bfm
jeras/CA-equivalence
brute-force rule equivalence search
jeras/fpga_synthesys_issues
Debugging FPGA synthesis issues, article and examples
jeras/HylocereusEmonica
Red Pitaya Ecosystem and Applications
jeras/HylocereusEmonica-jupyter
Python API and interactive web applications
jeras/jeras.github.io
personal "Rattus Pubis" webpage
jeras/libiio
Library for interfacing with IIO devices
jeras/Ne10
An open optimized software library project for the ARM® Architecture
jeras/readthedocs-source-links
Read the Docs issue with source links demo
jeras/red-pitaya-notes
My notes on the Red Pitaya Open Source Instrument
jeras/rv32_1stage_sv
improvized rv32_1stage translation from Chisel to SystemVerilog
jeras/test_lfs
test for GitHub LFS functionality, including locking
jeras/three.js
Displaying 2D CA (quad) preimage network
jeras/waveform_examples
A set of examples to be used by GTKWave for experimenting with SystemVerilog data types
jeras/zbus
symmetric low resource bus