jeras/synthesis-primitives

Observing and optimizing synthesis of common bit manipulation operations for FPGA and ASIC

Synthesis primitives

The document is divided into the following sections:

• logic primitives,
• multiplexer,
  • decoder/encoder,
  • one-hot/priority/thermometer encoding,
  • Gray encoder/decoder,
  • equivalence comparator,
  • population count,
• multiplexers,
  • shifter,
• arithmetic primitives,
  • magnitude comparator,
  • adder architectures,
  • multipliers,
  • ...
• coding theory primitives,
  • SECDED,
  • Hamming code,
  • ...
• sorting networks,
• interconnect
  • fixed priority and round-robin arbiters,
  • mask/range address decoder,
• VALID/READY handshake
  • Datapath register slice
  • Backpressure register slice
• pipelining
  • synchronous/asynchronous FIFO,
  • pipeline stages,
  • skid buffer,
• memories,
  • memory inference,
  • synchronous/asynchronous static RAM,
• ...

Each section contains a variety of RTL primitives and discusses them in terms of:

• syntax
  • Verilog, SystemVerilog and VHDL syntax,
  • parameterization/generalization,
  • inference,
  • iterative algorithms,
  • loop unwinding and vectorization,
  • recursion,
• simulation,
  • simulating combinational/sequential circuits,
  • achieving good coverage,
• synthesis
  • timing/area complexity
  • timing/area/power optimizations/compromises,
  • parallel prefix network structures,
  • ASIC specific optimizations (flip-flops without reset, clock gating, ...),
  • FPGA specific optimizations (fast carry chains, LUT size, ...).

License

If not stated otherwise, the documents are published under under CC BY 4.0