stnolting
"Roads? Where we're going we don't need roads." - Doc Brown
@Fraunhofer-IMS🇪🇺 European Union
Pinned Repositories
captouch
👇 Add capacitive touch buttons to any FPGA!
fpga_puf
:key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
fpga_torture
🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
neo430
:computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
neorv32
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
neorv32-riscof
✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
neorv32-setups
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
neoTRNG
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
riscv-gcc-prebuilt
📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
stnolting's Repositories
stnolting/neorv32
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
stnolting/neo430
:computer: A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
stnolting/neoTRNG
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
stnolting/fpga_puf
:key: Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
stnolting/captouch
👇 Add capacitive touch buttons to any FPGA!
stnolting/riscv-gcc-prebuilt
📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
stnolting/neorv32-setups
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
stnolting/neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
stnolting/fpga_torture
🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
stnolting/neorv32-riscof
✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
stnolting/wb_spi_bridge
🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
stnolting/cjtag_bridge
🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
stnolting/riscv-debug-dtm
🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.
stnolting/neorv32-formal
Formal verification (experiments) targeting the NEORV32 RISC-V processor.
stnolting/74xx_discrete_clock
A retro-style digital clock based on 74xx discrete logic chips
stnolting/neorv32-freertos
💾 FreeRTOS port for the NEORV32 RISC-V Processor.
stnolting/icarus-verilog-prebuilt
📦 Prebuilt Icarus Verilog simulator package for x64 Linux.
stnolting/neorv32_soc
Playing around with the [`neorv32`](https://github.com/stnolting/neorv32) SoC on a [Gecko4Education](https://gecko-wiki.ti.bfh.ch/gecko4education:start) Board with an Intel Cyclone IV E FPGA.
stnolting/risca
Arduino Platform for Embedded RISC-V Chips