rv32i
There are 113 repositories under rv32i topic.
darklife/darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
ultraembedded/riscv
RISC-V CPU Core (RV32IM)
sysprog21/shecc
A self-hosting and educational C optimizing compiler
syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
ultraembedded/biriscv
32-bit Superscalar RISC-V CPU
WangXuan95/USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
riscv-steel/riscv-steel
Open source RISC-V microcontroller unit for FPGAs written in Verilog
stnolting/riscv-gcc-prebuilt
📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
maikmerten/spu32
Small Processing Unit 32: A compact RV32I CPU written in Verilog
aignacio/nox
RISC-V Nox core
AngeloJacobo/RISC-V
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
sysprog21/rv32emu-legacy
RISC-V RV32I[MA] emulator with ELF support
panda5mt/KyogenRV
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
FelipeFFerreira/ITA-CORES
RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
rob-ng15/Silice-Playground
Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
saursin/riscv-atom
An open-source 32-bit RISC-V soft-core processor
kamiyaowl/rv32i-sim
RISC-V Software Simulation
martinKindall/risc-v-single-cycle
A Single Cycle Risc-V 32 bit CPU
RISCuinho/core
**RISC**uinho - A scratch in the possibilities in the universe of microcontrollers
accomdemy/accomdemy_rv32i
伴伴學 RISC-V RV32I Architecture CPU
enthusi/mandelbrot_riscv_assembler
An example in bare metal RV32 assembly for the longan nano board
kuby1412/RISC-V-MYTH-Workshop
This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
zeeshanrafique23/RV32I-Logisim
RV32I single cycle simulation on open-source software Logisim.
dpretet/friscv
RISCV CPU implementation in SystemVerilog
xarc/harv
HARV - HArdened Risc-V
djzenma/RV32IC-CPU
Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.
GabbedT/ApogeoRV
A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
franzflasch/leiwand_rv32
RISC-V RV32I CPU written in verilog
gafert/Apate
A graphical and educational processor simulator based on the RISC-V instruction set architecture
Undefined01/riscv
An FPGA-based RISC-V CPU
enthusi/lz4_rv32i_decode
LZ4 decoder in assembly for RiscV RV32IC
arhamhashmi01/rv32i-pipeline-processor
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
nobotro/fpga_riscv_cpu
fpga verilog risc-v rv32i cpu
strongwong/bittyCore_RISC-V
This is a bitty CPU core of risc-v architecture, which is currently under development.
bnossum/midgetv
rv32i/rv32im/rv32imc for iCE40. Wishbone interface.
paulsonkantony/risk-five
A Verilog based implementation of the unprivileged RV32I ISA