Redcrafter/verilog2factorio

Issues

• Feature Request: Operate on the entire vector of signals in a wire

  #24 opened 3 years ago by kotarou3
  1

• Compiled blueprint does not have expected behavior

  #17 opened 4 years ago by DaleStan
  1

• Attempts to Construct Overlong Wires

  #11 opened 4 years ago by MDFL64
  4

• Non-Deterministic Outputs

  #10 opened 4 years ago by MDFL64
  2

• Opaque error and stacktrace when unable to compile

  #9 opened 4 years ago by wordandahalf
  6

• What have you done?

  #8 opened 4 years ago by mohas
  1