Xilinx/Vitis_Model_Composer

Issues

• Sine wave HDL bug: output data can't be spectrum analyzed

  #37 opened 9 months ago by mohammadsdtmnd
  5

• Is SysGen now VitisModelComposer

  #16 opened 9 months ago by Beauxrel
  5

• Example HDL: AXI DDS Compiler, Simulink period set to 1 despite frequency is 1Mhz

  #36 opened 9 months ago by mohammadsdtmnd
  0

• Lab6 - XPAR_LAB6_1_0_DEVICE_ID in hello_world_final.c is not declared

  #20 opened a year ago by RaulAguilarOH
  1

• lab6_1.h is missing

  #19 opened a year ago by RaulAguilarOH
  1

• Running_BOOT_BIN_on_Hardware

  #15 opened 2 years ago by saraproctor
  1