Y-BoBo

Pinned Repositories

• 32-Verilog-Mini-Projects

  Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

  Language:Verilog0100

• AMBA_AXI_AHB_APB

  AMBA bus lecture material

  Language:Verilog00

• ariane

  Ariane is a 6-stage RISC-V CPU capable of booting Linux

  Language:SystemVerilog0100

• basic_verilog

  Must-have verilog systemverilog modules

  Language:Verilog0000

• bin2coe

  Binary data to Xilinx COE BRAM Converter

  0000

• busybear-linux

  busybear-linux is a tiny RISC-V Linux root filesystem image that targets the VirtIO board in riscv-qemu.

  Language:Shell10

• Cache-Replacement-Algorithm-Simulator

  Simulator similar to Champ sim which gives then hit ratio of a given algorithm with respect to a trace file

  Language:C00

• CampusShame

  互联网仍有记忆！那些曾经在校招过程中毁过口头offer、意向书、三方的公司！纵然人微言轻，也想尽绵薄之力！

  0000

• NF5

  A simple 5-stage Pipeline RISC-V core

  Language:Verilog1100

• RV32I-GPU

  RV32I Open Source GPU

  9106

Y-BoBo's Repositories