YiYao97

YiYao97's Stars

• kaitoukito/Computer-Science-Textbooks

  Collect some CS textbooks for learning.

  587165

• ShiArthur03/ShiArthur03

  Language:MATLAB10.4k1.9k

• veripool/verilog-mode

  Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

  Language:SystemVerilog26190

• chenzomi12/AISystem

  AISystem 主要是指AI系统，包括AI芯片、AI编译器、AI推理和训练框架等AI全栈底层技术

  Language:Jupyter Notebook11k1.6k

• tree-sitter/tree-sitter-verilog

  SystemVerilog grammar for tree-sitter

  Language:JavaScript9236

• projekt0n/github-nvim-theme

  GitHub's Neovim themes

  Language:Lua2.1k104

• HiPhish/rainbow-delimiters.nvim

  Rainbow delimiters for Neovim with Tree-sitter

  Language:Lua54640

• risclite/SuperScalar-RISCV-CPU

  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.

  Language:SystemVerilog19942

• tpope/vim-endwise

  endwise.vim: Wisely add

  Language:Vim Script1.1k102

• imc-trading/svlangserver

  Language:TypeScript10013

• sainnhe/sonokai

  High Contrast & Vivid Color Scheme based on Monokai Pro

  Language:Vim Script1.7k119

• zhuzhzh/verilog_emacsauto.vim

  verilog filetype plugin to enable emacs verilog-mode autos

  Language:Vim script2210

• mshr-h/vscode-verilog-hdl-support

  HDL support for VS Code

  Language:TypeScript29378

• jbush001/NyuziProcessor

  GPGPU microprocessor architecture

  Language:C2k353

• OpenXiangShan/difftest

  Modern co-simulation framework for RISC-V CPUs

  Language:C++11566

• alexforencich/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog1.5k447

• cyyself/soc-simulator

  A Verilator based SoC simulator that allows you to define AXI Slave interface in software.

  Language:C++427

• riscv-software-src/riscv-tests

  Language:C891458

• chipsalliance/riscv-dv

  Random instruction generator for RISC-V processor verification

  Language:Python1k328

• ultraembedded/biriscv

  32-bit Superscalar RISC-V CPU

  Language:Verilog859146

• shawn110285/Cookabarra

  a training-target implementation of rv32im, designed to be simple and easy to understand

  Language:Verilog5412

• ucb-bar/riscv-sodor

  educational microarchitectures for risc-v isa

  Language:Scala685155

• ultraembedded/riscv

  RISC-V CPU Core (RV32IM)

  Language:Verilog1.2k233

• RoaLogic/RV12

  RISC-V CPU Core

  Language:SystemVerilog28550

• rsd-devel/rsd

  RSD: RISC-V Out-of-Order Superscalar Processor

  Language:SystemVerilog98998

• ZipCPU/wb2axip

  Bus bridges and other odds and ends

  Language:Verilog484101