Pinned Repositories
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
DataAnalysis
udacity
FilltheBlank
Udacity Stage2
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
mavlink
Marshalling / communication library for drones.
MAVSDK
API and library for MAVLink compatible systems written in C++17
movie_library
Movie_Website
no-OS
Software drivers in C for systems without an operating system
openofdm
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
YideTian's Repositories
YideTian/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
YideTian/DataAnalysis
udacity
YideTian/FilltheBlank
Udacity Stage2
YideTian/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
YideTian/mavlink
Marshalling / communication library for drones.
YideTian/MAVSDK
API and library for MAVLink compatible systems written in C++17
YideTian/movie_library
YideTian/Movie_Website
YideTian/no-OS
Software drivers in C for systems without an operating system
YideTian/openofdm
Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.
YideTian/openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design
YideTian/openwifi-hw
FPGA (chip) design of openwifi (IEEE 802.11)
YideTian/u-boot-xlnx
The official Xilinx u-boot repository
YideTian/w25qxx
w25qxx full function driver
YideTian/verilog-axi
Verilog AXI components for FPGA implementation
YideTian/walkgeek
ARM Cortex-M4 MP3 and Opus audio player