Yong12315

Pinned Repositories

ADC-dynamic-parameter
Language:MATLAB00
MPSOC-DDR-TEST
test DDR spead of Zynq MPSoC by bare metal code
Language:C00
UVM
Language:SystemVerilog00
ZYNQ_module
there are some useful modul which used frequently in ZYNQ
Language:Verilog00

Yong12315's Repositories

Yong12315/UVM
Language:SystemVerilog
Yong12315/ADC-dynamic-parameter
Language:MATLAB
Yong12315/MPSOC-DDR-TEST
test DDR spead of Zynq MPSoC by bare metal code
Language:C
Yong12315/ZYNQ_module
there are some useful modul which used frequently in ZYNQ
Language:Verilog