Yu-An-Shih

Pinned Repositories

autoGenILA
Automatic generation of architecture-level models for hardware from its RTL design.
Language:Verilog00
biriscv
32-bit Superscalar RISC-V CPU
Language:Verilog00
byoc
The OpenPiton Platform
Language:Assembly00
Cores-SweRV
SweRV EH1 core
Language:SystemVerilog00
deit
COS598D final project
Language:Python00
DynamicViT
[NeurIPS 2021] DynamicViT: Efficient Vision Transformers with Dynamic Token Sparsification
Language:Jupyter Notebook0 0 00
llvm-project
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.
0 0 00
mallob
Malleable Load Balancer. Massively Parallel Logic Backend. Award-winning SAT solving for the cloud.
Language:C++00
openpiton
ECE575 final project
Language:Assembly0 1 00
PartRet
Language:Verilog1 1 00

Yu-An-Shih's Repositories

Yu-An-Shih/PartRet
Language:Verilog1 1 00
Yu-An-Shih/autoGenILA
Automatic generation of architecture-level models for hardware from its RTL design.
Language:Verilog00
Yu-An-Shih/biriscv
32-bit Superscalar RISC-V CPU
Language:Verilog00
Yu-An-Shih/byoc
The OpenPiton Platform
Language:Assembly00
Yu-An-Shih/Cores-SweRV
SweRV EH1 core
Language:SystemVerilog00
Yu-An-Shih/deit
COS598D final project
Language:Python00
Yu-An-Shih/DynamicViT
[NeurIPS 2021] DynamicViT: Efficient Vision Transformers with Dynamic Token Sparsification
Language:Jupyter Notebook0 0 00
Yu-An-Shih/llvm-project
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this moment. Please submit your patches at http://reviews.llvm.org.
0 0 00
Yu-An-Shih/mallob
Malleable Load Balancer. Massively Parallel Logic Backend. Award-winning SAT solving for the cloud.
Language:C++00
Yu-An-Shih/openpiton
ECE575 final project
Language:Assembly0 1 00
Yu-An-Shih/Yosys_extensions
Language:C++