Design with Logisim a 32-bit two-cycle processor
I did this project for CS61C at UC Berkeley (Spring 2015): http://www-inst.eecs.berkeley.edu/~cs61c/sp15/projs/02/index.html
The processor contains four major parts: register files, arithmetic logical unit (ALU), CPU and memory. The instruction set architecture (ISA) is specified in the above link.