ASIC Design Flow

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Chip Design Flow

A typical design flow follows a structure shown below and can be broken down into multiple steps. Some of these phases happen in parallel and some sequentially. We'll take a look at how a typical project design cycle looks like in the industry today.

Pre-Requisites

Documentation

Lectures

Execution

Create a design in Verilog language, change the directory to OpenLane, and then follow these steps:

1. Creating Container

make mount

2. Initializing ASIC Flow

./flow.tcl -design <folder_name> -add_to_designs -init_design_config

3. Creating Design File

Move to the folder designs containing <folder_name>.
Open the file config.json and edit the details mentioned according to the design file.
Move to the folder src and create your design file in that folder.

4. Initiating ASIC Flow

Change the directory to OpenLane and run the following commands:

./flow.tcl -design <folder_name> -tag first_run -interactive

Step 1: Synthesis

run_synthesis

Step 2: Floorplan

run_floorplan

Step 3: Placement

run_placement

Step 4: Clock Tree Synthesis

run_cts

Step 5: Routing

run_routing

Step 6: GDS Generation

run_magic

Step 7: Creating Netlist of GDS

run_magic_spice_export

Step 8: DRC

run_magic_drc

Step 9: LVS

run_lvs

Step 10: Antenna Check

run_antenna_check

5. Exiting ASIC Flow

exit

Instructor

Sajjad Ahmed

ZAIN-ALI-02/ASIC_Design_Flow