ASIC_LearnHub: Your gateway to mastering ASIC design! Explore curated resources and examples for learning ASIC workflows. Ideal for students and novice engineers. Join us at ASIC_LearnHub to turbocharge your journey into the exciting world of ASICs! 🚀 #ASIC #LearnASIC
A typical design flow follows a structure shown below and can be broken down into multiple steps. Some of these phases happen in parallel and some sequentially. We'll take a look at how a typical project design cycle looks like in the industry today.
Create a design in Verilog language, change the directory to OpenLane
, and then follow these steps:
make mount
./flow.tcl -design <folder_name> -add_to_designs -init_design_config
- Move to the folder
designs
containing<folder_name>
. - Open the file
config.json
and edit the details mentioned according to the design file. - Move to the folder
src
and create your design file in that folder.
Change the directory to OpenLane
and run the following commands:
./flow.tcl -design <folder_name> -tag first_run -interactive
run_synthesis
run_floorplan
run_placement
run_cts
run_routing
run_magic
run_magic_spice_export
run_magic_drc
run_lvs
run_antenna_check
exit