ZPNMiaoHeng

A lazy man.

QUSTChina

Pinned Repositories

aes
Language:Verilog00
am-kernels
00
am-kernels-6
Language:C00
chipyard
Language:C00
CPP
Lecture notes, projects and other materials for Course 'CS205 C/C++ Program Design' at Southern University of Science and Technology.
Language:C++10
drawioFolder
00
e203
Study
Language:Verilog00
Hash
Language:C10
NutShell
RISC-V SoC designed by students in UCAS
Language:Scala10
tinyriscv_v
Language:C10

ZPNMiaoHeng's Repositories

ZPNMiaoHeng/CPP
Lecture notes, projects and other materials for Course 'CS205 C/C++ Program Design' at Southern University of Science and Technology.
Language:C++10
ZPNMiaoHeng/Hash
Language:C10
ZPNMiaoHeng/NutShell
RISC-V SoC designed by students in UCAS
Language:Scala10
ZPNMiaoHeng/tinyriscv_v
Language:C10
ZPNMiaoHeng/aes
Language:Verilog00
ZPNMiaoHeng/am-kernels
00
ZPNMiaoHeng/am-kernels-6
Language:C00
ZPNMiaoHeng/chipyard
Language:C00
ZPNMiaoHeng/drawioFolder
00
ZPNMiaoHeng/e203
Study
Language:Verilog00
ZPNMiaoHeng/e203_qust
Language:C
ZPNMiaoHeng/gem5
Language:C++
ZPNMiaoHeng/iEDA-data-set
Language:Verilog
ZPNMiaoHeng/lazy_nvim
Language:Lua
ZPNMiaoHeng/llm.c
LLM training in simple, raw C/CUDA
ZPNMiaoHeng/neorv32
Language:VHDL
ZPNMiaoHeng/neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
Language:Verilog
ZPNMiaoHeng/opene902
Language:Verilog
ZPNMiaoHeng/OSCPU
Language:Verilog
ZPNMiaoHeng/rCore-Tutorial-v3
Let's write an OS which can run on RISC-V in Rust from scratch!
ZPNMiaoHeng/riscvmini
Language:Scala
ZPNMiaoHeng/rocket-chip
Rocket Chip Generator
ZPNMiaoHeng/rt-thread
RT-Thread is an open source IoT real-time operating system (RTOS).
ZPNMiaoHeng/SparrowRV
Language:C
ZPNMiaoHeng/tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
ZPNMiaoHeng/tinyriscv
Language:C
ZPNMiaoHeng/yosys-sta
Language:Verilog
ZPNMiaoHeng/ysyx-workbench
Language:C
ZPNMiaoHeng/yxyx_ZPN
It is use to study
Language:C++