Za-i-ra

Pinned Repositories

UninaSoC
RISC-V SoC design for FPGA fast prototyping from University of Naples Federico II
Language:SystemVerilog03
T6-G8
Requisiti Sull’Editor di Test Case
Language:JavaScript00
UninaSoC
RISC-V SoC design for FPGA fast prototyping from University of Naples Federico II
Language:Tcl00

Za-i-ra's Repositories

Za-i-ra/UninaSoC
RISC-V SoC design for FPGA fast prototyping from University of Naples Federico II
Language:Tcl00