ZheChen-Bill

Pinned Repositories

• SoC_Design_Lab4_1

  Language:Verilog10

• ASoC_catapult

  Language:Verilog00

• ASoC_fsic_sim

  Language:Verilog00

• ASoC_lab4_FSIC_FPGA

  ASoC_lab4_FSIC_FPGA

  Language:VHDL00

• caravel-soc_fpga-lab

  Language:VHDL00

• convolution-filtering

  Language:C++00

• DSPIC_Final

  Language:Verilog00

• DSPIC_HW4

  first commit

  Language:Verilog00

• HLS_FINAL

  Language:C++00

• Interface_Synthesis

  Language:Ada00

ZheChen-Bill's Repositories