i2c_master.v //Master verilog design. i2c_slave.v //Slave verilog design. i2c_tb.v //Original testbench. i2c_read_tb.v //Read function testbench i2c_read2_tb.v //Master clock 100kHz(10us), slave clock work range 167kHz(6us)-24kHz(42us), SCL 1kHz. i2c_write_tb.v //Wirte function testbench. i2c_write2_tb.v //Master clock 100kHz(10us), slave clock work range 167kHz(6us)-24kHz(42us), SCL 1kHz. i2c.v //Combine master and slave. i2c_block_write_tb.v //Combine block write testbench. i2c_block_read_tb.v //Combine block read testbench.