ZhixuanChang

Zhejiang UniversityHangzhou, Zhejiang Province, China

Pinned Repositories

AXI4_Interconnect
AXI总线连接器
Language:SystemVerilog0 0 00
ddr3-controller
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
Language:Verilog0 0 00
hellopages
test GitHub pages
Language:HTML00
LaTeX_temp
Some LaTeX templates used for articles and reports.
Language:TeX0 1 00
STM32H7Workspace
STM32Cube MCU Full Package for the STM32H7 series - (HAL + LL Drivers, CMSIS Core, CMSIS Device, MW libraries plus a set of Projects running on all boards provided by ST (Nucleo, Evaluation and Discovery Kits))
Language:C0 0 00
zhixuanchang.github.io
blog of ZhixuanChang
Language:HTML0 1 00
zjuthesis
Zhejiang University Graduation Thesis LaTeX Template
Language:TeX0 0 00

ZhixuanChang/AXI4_Interconnect
AXI总线连接器
Language:SystemVerilog0 0 00
ZhixuanChang/ddr3-controller
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
Language:Verilog0 0 00
ZhixuanChang/hellopages
test GitHub pages
Language:HTML00
ZhixuanChang/LaTeX_temp
Some LaTeX templates used for articles and reports.
Language:TeX0 1 00
ZhixuanChang/STM32H7Workspace
STM32Cube MCU Full Package for the STM32H7 series - (HAL + LL Drivers, CMSIS Core, CMSIS Device, MW libraries plus a set of Projects running on all boards provided by ST (Nucleo, Evaluation and Discovery Kits))
Language:C0 0 00
ZhixuanChang/zhixuanchang.github.io
blog of ZhixuanChang
Language:HTML0 1 00
ZhixuanChang/zjuthesis
Zhejiang University Graduation Thesis LaTeX Template
Language:TeX0 0 00