UT-Backplane-mapping

Signal mapping netlist (list of pin-to-pin correspondence) formatted for Altium to design the LHCb UT backplane.

AltiumNetlistGen.py: This script takes 3 YAML files and write the reformatted list to output/. All YAML files are located under input/; one of them describes connections from PT connectors point-of-view (PT- DCB); another from DCB; the third one includes break-out boards pin assignments.
NetlistCheck.py: This scripts takes Altium-exported netlists (under input/netlists) and check if these netlists fully implements connections specified in the copy-paste lists generated by the script above.
FiberAsicMap.py: This scripts take parsed netlists from AltiumNetlistGen.py, then use pre-defined PEPI structure in pyUTM.common to generate ASIC to fiber mapping in output/.

Prerequisite

Install the dependencies:

pip install -r pyUTM/requirements.txt

If only the copy-and-paste .csv are needed:

python ./AltiumNetlistGen.py

If additional error checking is required (note that this script would also generate .csv files):

python ./NetlistCheck.py <path_to_netlist_file> <optional:log_filename>

if <log_filename> not provided, log will be generated under log/, with a time-stamped filename of NetlistCheck-<bp_type>-YYYY-MM-DD-HHMMSS.log

If additional ASIC to fiber mapping generation is required:

python ./FiberAsicMap.py

All generated .csv files are located under output/. These scripts print out warnings to stdout, and can be redirected as needed.

The backplane-mapping effort is documented on TWiki page: 1